| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 157 const MCOperand Op1 = MI.getOperand(1);
158 assert(Op1.isReg() && "First operand is not register.");
159 Encoding = MRI.getEncodingValue(Op1.getReg());
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 102 MachineOperand &Op1 = MI->getOperand(1);
113 NewMI->addOperand(Op1);
145 MachineOperand &Op1 = MI->getOperand(1);
155 NewMI->addOperand(Op1);
187 MachineOperand &Op1 = MI->getOperand(1);
196 NewMI->addOperand(Op1);
224 MachineOperand &Op1 = MI->getOperand(1);
234 NewMI->addOperand(Op1);
|
| HexagonPeephole.cpp | 290 MachineOperand Op1 = MI->getOperand(S1);
293 ChangeOpInto(MI->getOperand(S2), Op1);
|
| HexagonCopyToCombine.cpp | 121 const MachineOperand &Op1 = MI->getOperand(1);
122 assert(Op0.isReg() && Op1.isReg());
125 unsigned SrcReg = Op1.getReg();
134 const MachineOperand &Op1 = MI->getOperand(1);
141 if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
145 bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm());
|
| HexagonSplitDouble.cpp | 672 MachineOperand &Op1 = MI->getOperand(1);
673 assert(Op0.isReg() && Op1.isImm());
674 uint64_t V = Op1.getImm();
700 MachineOperand &Op1 = MI->getOperand(1);
710 if (Op1.isImm()) {
712 .addImm(Op1.getImm());
713 } else if (Op1.isReg()) {
715 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg())
[all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 858 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
867 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
870 Ops[2].getAsInteger(10, Op1);
874 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
900 uint32_t Op1 = (Bits >> 11) & 0x7;
905 return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
|
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 205 const MachineOperand *Op1 = &MI1.getOperand(N1 + X86::AddrDisp);
207 if (!isIdenticalOp(*Op1, *Op2)) {
208 if (Op1->isImm() && Op2->isImm())
209 AddrDispShift = Op1->getImm() - Op2->getImm();
210 else if (Op1->isGlobal() && Op2->isGlobal() &&
211 Op1->getGlobal() == Op2->getGlobal())
212 AddrDispShift = Op1->getOffset() - Op2->getOffset();
|
| X86FloatingPoint.cpp | [all...] |
| X86MCInstLower.cpp | 323 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
328 if (Op0 == X86::AX && Op1 == X86::AL)
332 if (Op0 == X86::EAX && Op1 == X86::AX)
336 if (Op0 == X86::RAX && Op1 == X86::EAX)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 195 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
196 if (!Op1) return false;
208 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, C);
347 Constant *Op1 = dyn_cast<Constant>(C->getOperand(1));
348 if (!Op1) return nullptr;
351 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, At);
|
| Scalarizer.cpp | 74 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1,
76 return Builder.CreateFCmp(FCI.getPredicate(), Op0, Op1, Name);
85 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1,
87 return Builder.CreateICmp(ICI.getPredicate(), Op0, Op1, Name);
96 Value *operator()(IRBuilder<> &Builder, Value *Op0, Value *Op1,
98 return Builder.CreateBinOp(BO.getOpcode(), Op0, Op1, Name);
382 Scatterer Op1 = scatter(&I, I.getOperand(1));
384 assert(Op1.size() == NumElems && "Mismatched binary operation");
388 Res[Elem] = Split(Builder, Op0[Elem], Op1[Elem],
401 Scatterer Op1 = scatter(&SI, SI.getOperand(1))
[all...] |
| /external/llvm/lib/DebugInfo/DWARF/ |
| DWARFDebugFrame.cpp | 110 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK;
115 addInstruction(Primary, Op1);
118 addInstruction(Primary, Op1, Data.getULEB128(Offset));
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 286 SDValue Op0, Op1;
290 if (!SelectAddr(Op, Op0, Op1))
296 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 390 SDValue Op0, Op1;
395 if (!SelectADDRrr(Op, Op0, Op1))
396 SelectADDRri(Op, Op0, Op1);
401 OutOps.push_back(Op1);
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
347 unsigned Op1, Op2;
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
360 unsigned Op1, Op2;
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
365 Inst.addOperand(MCOperand::createImm(Op1));
[all...] |
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 569 Value *Op1 = CI->getArgOperand(1);
580 Rep = Builder.CreateShuffleVector(Op0, Op1, ConstantVector::get(Idxs));
586 Value *Op1 = CI->getArgOperand(1);
595 Value *UndefV = UndefValue::get(Op1->getType());
600 Rep = Builder.CreateShuffleVector(Op1, UndefV, ConstantVector::get(Idxs));
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
34 if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
38 if (Constant *CUI = dyn_cast<Constant>(Op1))
46 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
50 Op1->getName());
321 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
326 if (ConstantDataVector *CV = dyn_cast<ConstantDataVector>(Op1))
328 else if (ConstantVector *CV = dyn_cast<ConstantVector>(Op1))
331 COp1 = dyn_cast<ConstantInt>(Op1);
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 67 const MCOperand &Op1 = MI->getOperand(1);
100 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
136 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
145 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
153 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
160 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 323 const MachineOperand &Op1 = I->getOperand(1);
326 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
348 unsigned SrcReg = Op1.getReg();
365 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 735 SDValue Op1 = Op.getOperand(1);
739 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
772 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
779 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
781 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 565 const MachineOperand &Op1 = Inst.getOperand(1);
573 if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
574 MI1 = MRI.getUniqueVRegDef(Op1.getReg());
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 900 SDValue Op1 = N->getOperand(1);
964 if (SelectDirectAddr(Op1, Addr)) {
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 414 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
415 // between the base and index. Try to fold Op1 into AM's displacement.
417 SDValue Op0, uint64_t Op1) {
419 int64_t TestDisp = AM.Disp + Op1;
441 SDValue Op1 = N.getOperand(1);
444 unsigned Op1Code = Op1->getOpcode();
447 return expandAdjDynAlloc(AM, IsBase, Op1);
452 return expandDisp(AM, IsBase, Op1,
456 cast<ConstantSDNode>(Op1)->getSExtValue());
458 if (IsBase && expandIndex(AM, Op0, Op1))
[all...] |
| SystemZISelLowering.cpp | 45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
48 SDValue Op0, Op1;
50 // The opcode that should be used to compare Op0 and Op1.
[all...] |
