| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 87 const unsigned ShiftAmt = ToIdx * 16;
90 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
92 Imm &= ~(0xFFFFLL << ShiftAmt);
104 const unsigned ShiftAmt = ChunkIdx * 16;
124 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
185 unsigned ShiftAmt = 0;
188 for (; ShiftAmt < 64; ShiftAmt += 16) {
189 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
202 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
[all...] |
| AArch64ConditionOptimizer.cpp | 158 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm());
162 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
|
| AArch64ISelDAGToDAG.cpp | 260 unsigned ShiftAmt;
263 ShiftAmt = 0;
265 ShiftAmt = 12;
270 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| DemandedBits.cpp | 145 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1);
146 AB = AOut.lshr(ShiftAmt);
152 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
154 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
161 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1);
162 AB = AOut.shl(ShiftAmt);
167 AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
174 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1);
175 AB = AOut.shl(ShiftAmt);
179 if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
[all...] |
| ConstantFolding.cpp | 176 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1);
187 ConstantInt::get(Src->getType(), ShiftAmt));
188 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
208 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1);
213 ConstantInt::get(Src->getType(), ShiftAmt));
214 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
[all...] |
| ValueTracking.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 567 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
568 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
573 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
575 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
581 KnownZero <<= ShiftAmt;
582 KnownOne <<= ShiftAmt;
584 if (ShiftAmt)
585 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
591 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
594 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
[all...] |
| InstCombineCalls.cpp | 298 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth));
299 auto ShiftVec = Builder.CreateVectorSplat(VWidth, ShiftAmt);
[all...] |
| InstCombineCasts.cpp | 642 uint32_t ShiftAmt = KnownZeroMask.logBase2();
644 if (ShiftAmt) {
645 // Perform a logical shr by shiftamt.
647 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt),
784 uint64_t ShiftAmt = Amt->getZExtValue();
785 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0;
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | [all...] |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyCFG.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
