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      1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "Hexagon.h"
     11 #include "MCTargetDesc/HexagonBaseInfo.h"
     12 #include "MCTargetDesc/HexagonFixupKinds.h"
     13 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
     14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
     15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
     16 #include "llvm/ADT/Statistic.h"
     17 #include "llvm/MC/MCCodeEmitter.h"
     18 #include "llvm/MC/MCContext.h"
     19 #include "llvm/MC/MCExpr.h"
     20 #include "llvm/MC/MCInst.h"
     21 #include "llvm/MC/MCInstrInfo.h"
     22 #include "llvm/MC/MCRegisterInfo.h"
     23 #include "llvm/MC/MCSubtargetInfo.h"
     24 #include "llvm/Support/Debug.h"
     25 #include "llvm/Support/EndianStream.h"
     26 #include "llvm/Support/raw_ostream.h"
     27 
     28 #define DEBUG_TYPE "mccodeemitter"
     29 
     30 using namespace llvm;
     31 using namespace Hexagon;
     32 
     33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
     34 
     35 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
     36                                            MCContext &aMCT)
     37     : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
     38       Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
     39 
     40 uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
     41                                          MCInst const &MCB,
     42                                          MCInst const &MCI) const {
     43   bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
     44   if (Instruction == 0) {
     45     if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
     46       assert(!Duplex);
     47       assert(Instruction != Last);
     48       return HexagonII::INST_PARSE_LOOP_END;
     49     }
     50   }
     51   if (Instruction == 1) {
     52     if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
     53       assert(!Duplex);
     54       assert(Instruction != Last);
     55       return HexagonII::INST_PARSE_LOOP_END;
     56     }
     57   }
     58   if (Duplex) {
     59     assert(Instruction == Last);
     60     return HexagonII::INST_PARSE_DUPLEX;
     61   }
     62   if(Instruction == Last)
     63     return HexagonII::INST_PARSE_PACKET_END;
     64   return HexagonII::INST_PARSE_NOT_END;
     65 }
     66 
     67 void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
     68                                              SmallVectorImpl<MCFixup> &Fixups,
     69                                              MCSubtargetInfo const &STI) const {
     70   MCInst &HMB = const_cast<MCInst &>(MI);
     71 
     72   assert(HexagonMCInstrInfo::isBundle(HMB));
     73   DEBUG(dbgs() << "Encoding bundle\n";);
     74   *Addend = 0;
     75   *Extended = false;
     76   *CurrentBundle = &MI;
     77   size_t Instruction = 0;
     78   size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
     79   for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
     80     MCInst &HMI = const_cast<MCInst &>(*I.getInst());
     81     EncodeSingleInstruction(HMI, OS, Fixups, STI,
     82                             parseBits(Instruction, Last, HMB, HMI),
     83                             Instruction);
     84     *Extended = HexagonMCInstrInfo::isImmext(HMI);
     85     *Addend += HEXAGON_INSTR_SIZE;
     86     ++Instruction;
     87   }
     88   return;
     89 }
     90 
     91 /// EncodeSingleInstruction - Emit a single
     92 void HexagonMCCodeEmitter::EncodeSingleInstruction(
     93     const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
     94     const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
     95   MCInst HMB = MI;
     96   assert(!HexagonMCInstrInfo::isBundle(HMB));
     97   uint64_t Binary;
     98 
     99   // Compound instructions are limited to using registers 0-7 and 16-23
    100   // and here we make a map 16-23 to 8-15 so they can be correctly encoded.
    101   static unsigned RegMap[8] = {Hexagon::R8,  Hexagon::R9,  Hexagon::R10,
    102                                Hexagon::R11, Hexagon::R12, Hexagon::R13,
    103                                Hexagon::R14, Hexagon::R15};
    104 
    105   // Pseudo instructions don't get encoded and shouldn't be here
    106   // in the first place!
    107   assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
    108          "pseudo-instruction found");
    109   DEBUG(dbgs() << "Encoding insn"
    110                   " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
    111                                                                     "\n");
    112 
    113   if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
    114     for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
    115       if (HMB.getOperand(i).isReg()) {
    116         unsigned Reg =
    117             MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg());
    118         if ((Reg <= 23) && (Reg >= 16))
    119           HMB.getOperand(i).setReg(RegMap[Reg - 16]);
    120       }
    121   }
    122 
    123   if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
    124     // Calculate the new value distance to the associated producer
    125     MCOperand &MCO =
    126         HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB));
    127     unsigned SOffset = 0;
    128     unsigned Register = MCO.getReg();
    129     unsigned Register1;
    130     auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
    131     auto i = Instructions.begin() + Index - 1;
    132     for (;; --i) {
    133       assert(i != Instructions.begin() - 1 && "Couldn't find producer");
    134       MCInst const &Inst = *i->getInst();
    135       if (HexagonMCInstrInfo::isImmext(Inst))
    136         continue;
    137       ++SOffset;
    138       Register1 =
    139           HexagonMCInstrInfo::hasNewValue(MCII, Inst)
    140               ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
    141               : static_cast<unsigned>(Hexagon::NoRegister);
    142       if (Register != Register1)
    143         // This isn't the register we're looking for
    144         continue;
    145       if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
    146         // Producer is unpredicated
    147         break;
    148       assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) &&
    149              "Unpredicated consumer depending on predicated producer");
    150       if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
    151           HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB))
    152         // Producer predicate sense matched ours
    153         break;
    154     }
    155     // Hexagon PRM 10.11 Construct Nt from distance
    156     unsigned Offset = SOffset;
    157     Offset <<= 1;
    158     MCO.setReg(Offset + Hexagon::R0);
    159   }
    160 
    161   Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
    162   // Check for unimplemented instructions. Immediate extenders
    163   // are encoded as zero, so they need to be accounted for.
    164   if ((!Binary) &&
    165       ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
    166        (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
    167        (HMB.getOpcode() != A4_ext_g))) {
    168     // Use a A2_nop for unimplemented instructions.
    169     DEBUG(dbgs() << "Unimplemented inst: "
    170                     " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
    171                                                                       "\n");
    172     llvm_unreachable("Unimplemented Instruction");
    173   }
    174   Binary |= Parse;
    175 
    176   // if we need to emit a duplexed instruction
    177   if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
    178       HMB.getOpcode() <= Hexagon::DuplexIClassF) {
    179     assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
    180            "Emitting duplex without duplex parse bits");
    181     unsigned dupIClass;
    182     switch (HMB.getOpcode()) {
    183     case Hexagon::DuplexIClass0:
    184       dupIClass = 0;
    185       break;
    186     case Hexagon::DuplexIClass1:
    187       dupIClass = 1;
    188       break;
    189     case Hexagon::DuplexIClass2:
    190       dupIClass = 2;
    191       break;
    192     case Hexagon::DuplexIClass3:
    193       dupIClass = 3;
    194       break;
    195     case Hexagon::DuplexIClass4:
    196       dupIClass = 4;
    197       break;
    198     case Hexagon::DuplexIClass5:
    199       dupIClass = 5;
    200       break;
    201     case Hexagon::DuplexIClass6:
    202       dupIClass = 6;
    203       break;
    204     case Hexagon::DuplexIClass7:
    205       dupIClass = 7;
    206       break;
    207     case Hexagon::DuplexIClass8:
    208       dupIClass = 8;
    209       break;
    210     case Hexagon::DuplexIClass9:
    211       dupIClass = 9;
    212       break;
    213     case Hexagon::DuplexIClassA:
    214       dupIClass = 10;
    215       break;
    216     case Hexagon::DuplexIClassB:
    217       dupIClass = 11;
    218       break;
    219     case Hexagon::DuplexIClassC:
    220       dupIClass = 12;
    221       break;
    222     case Hexagon::DuplexIClassD:
    223       dupIClass = 13;
    224       break;
    225     case Hexagon::DuplexIClassE:
    226       dupIClass = 14;
    227       break;
    228     case Hexagon::DuplexIClassF:
    229       dupIClass = 15;
    230       break;
    231     default:
    232       llvm_unreachable("Unimplemented DuplexIClass");
    233       break;
    234     }
    235     // 29 is the bit position.
    236     // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
    237     // Last bit is moved to bit position 13
    238     Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
    239 
    240     const MCInst *subInst0 = HMB.getOperand(0).getInst();
    241     const MCInst *subInst1 = HMB.getOperand(1).getInst();
    242 
    243     // get subinstruction slot 0
    244     unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
    245     // get subinstruction slot 1
    246     unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
    247 
    248     Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
    249   }
    250   support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
    251   ++MCNumEmitted;
    252 }
    253 
    254 static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
    255                                       const MCOperand &MO,
    256                                       const MCSymbolRefExpr::VariantKind kind) {
    257   const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
    258   unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
    259 
    260   if (insnType == HexagonII::TypePREFIX) {
    261     switch (kind) {
    262     case llvm::MCSymbolRefExpr::VK_GOTOFF:
    263       return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
    264     case llvm::MCSymbolRefExpr::VK_GOT:
    265       return Hexagon::fixup_Hexagon_GOT_32_6_X;
    266     case llvm::MCSymbolRefExpr::VK_TPREL:
    267       return Hexagon::fixup_Hexagon_TPREL_32_6_X;
    268     case llvm::MCSymbolRefExpr::VK_DTPREL:
    269       return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
    270     case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
    271       return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
    272     case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
    273       return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
    274     case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
    275       return Hexagon::fixup_Hexagon_IE_32_6_X;
    276     case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
    277       return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
    278     default:
    279       if (MCID.isBranch())
    280         return Hexagon::fixup_Hexagon_B32_PCREL_X;
    281       else
    282         return Hexagon::fixup_Hexagon_32_6_X;
    283     }
    284   } else if (MCID.isBranch())
    285     return (Hexagon::fixup_Hexagon_B13_PCREL);
    286 
    287   switch (MCID.getOpcode()) {
    288   case Hexagon::HI:
    289   case Hexagon::A2_tfrih:
    290     switch (kind) {
    291     case llvm::MCSymbolRefExpr::VK_GOT:
    292       return Hexagon::fixup_Hexagon_GOT_HI16;
    293     case llvm::MCSymbolRefExpr::VK_GOTOFF:
    294       return Hexagon::fixup_Hexagon_GOTREL_HI16;
    295     case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
    296       return Hexagon::fixup_Hexagon_GD_GOT_HI16;
    297     case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
    298       return Hexagon::fixup_Hexagon_LD_GOT_HI16;
    299     case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
    300       return Hexagon::fixup_Hexagon_IE_HI16;
    301     case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
    302       return Hexagon::fixup_Hexagon_IE_GOT_HI16;
    303     case llvm::MCSymbolRefExpr::VK_TPREL:
    304       return Hexagon::fixup_Hexagon_TPREL_HI16;
    305     case llvm::MCSymbolRefExpr::VK_DTPREL:
    306       return Hexagon::fixup_Hexagon_DTPREL_HI16;
    307     default:
    308       return Hexagon::fixup_Hexagon_HI16;
    309     }
    310 
    311   case Hexagon::LO:
    312   case Hexagon::A2_tfril:
    313     switch (kind) {
    314     case llvm::MCSymbolRefExpr::VK_GOT:
    315       return Hexagon::fixup_Hexagon_GOT_LO16;
    316     case llvm::MCSymbolRefExpr::VK_GOTOFF:
    317       return Hexagon::fixup_Hexagon_GOTREL_LO16;
    318     case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
    319       return Hexagon::fixup_Hexagon_GD_GOT_LO16;
    320     case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
    321       return Hexagon::fixup_Hexagon_LD_GOT_LO16;
    322     case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
    323       return Hexagon::fixup_Hexagon_IE_LO16;
    324     case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
    325       return Hexagon::fixup_Hexagon_IE_GOT_LO16;
    326     case llvm::MCSymbolRefExpr::VK_TPREL:
    327       return Hexagon::fixup_Hexagon_TPREL_LO16;
    328     case llvm::MCSymbolRefExpr::VK_DTPREL:
    329       return Hexagon::fixup_Hexagon_DTPREL_LO16;
    330     default:
    331       return Hexagon::fixup_Hexagon_LO16;
    332     }
    333 
    334   // The only relocs left should be GP relative:
    335   default:
    336     if (MCID.mayStore() || MCID.mayLoad()) {
    337       for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
    338            ++ImpUses) {
    339         if (*ImpUses == Hexagon::GP) {
    340           switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
    341           case HexagonII::MemAccessSize::ByteAccess:
    342             return fixup_Hexagon_GPREL16_0;
    343           case HexagonII::MemAccessSize::HalfWordAccess:
    344             return fixup_Hexagon_GPREL16_1;
    345           case HexagonII::MemAccessSize::WordAccess:
    346             return fixup_Hexagon_GPREL16_2;
    347           case HexagonII::MemAccessSize::DoubleWordAccess:
    348             return fixup_Hexagon_GPREL16_3;
    349           default:
    350             llvm_unreachable("unhandled fixup");
    351           }
    352         }
    353       }
    354     } else
    355       llvm_unreachable("unhandled fixup");
    356   }
    357 
    358   return LastTargetFixupKind;
    359 }
    360 
    361 namespace llvm {
    362 extern const MCInstrDesc HexagonInsts[];
    363 }
    364 
    365 namespace {
    366   bool isPCRel (unsigned Kind) {
    367     switch(Kind){
    368     case fixup_Hexagon_B22_PCREL:
    369     case fixup_Hexagon_B15_PCREL:
    370     case fixup_Hexagon_B7_PCREL:
    371     case fixup_Hexagon_B13_PCREL:
    372     case fixup_Hexagon_B9_PCREL:
    373     case fixup_Hexagon_B32_PCREL_X:
    374     case fixup_Hexagon_B22_PCREL_X:
    375     case fixup_Hexagon_B15_PCREL_X:
    376     case fixup_Hexagon_B13_PCREL_X:
    377     case fixup_Hexagon_B9_PCREL_X:
    378     case fixup_Hexagon_B7_PCREL_X:
    379     case fixup_Hexagon_32_PCREL:
    380     case fixup_Hexagon_PLT_B22_PCREL:
    381     case fixup_Hexagon_GD_PLT_B22_PCREL:
    382     case fixup_Hexagon_LD_PLT_B22_PCREL:
    383     case fixup_Hexagon_6_PCREL_X:
    384       return true;
    385     default:
    386       return false;
    387     }
    388   }
    389 }
    390 
    391 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
    392                                               const MCOperand &MO,
    393                                               const MCExpr *ME,
    394                                               SmallVectorImpl<MCFixup> &Fixups,
    395                                               const MCSubtargetInfo &STI) const
    396 
    397 {
    398   int64_t Res;
    399 
    400   if (ME->evaluateAsAbsolute(Res))
    401     return Res;
    402 
    403   MCExpr::ExprKind MK = ME->getKind();
    404   if (MK == MCExpr::Constant) {
    405     return cast<MCConstantExpr>(ME)->getValue();
    406   }
    407   if (MK == MCExpr::Binary) {
    408     getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getLHS(), Fixups, STI);
    409     getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getRHS(), Fixups, STI);
    410     return 0;
    411   }
    412 
    413   assert(MK == MCExpr::SymbolRef);
    414 
    415   Hexagon::Fixups FixupKind =
    416       Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
    417   const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
    418   const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
    419   unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
    420                   HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
    421   const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
    422 
    423   DEBUG(dbgs() << "----------------------------------------\n");
    424   DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
    425                << "\n");
    426   DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
    427   DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
    428   DEBUG(dbgs() << "Addend: " << *Addend << "\n");
    429   DEBUG(dbgs() << "----------------------------------------\n");
    430 
    431   switch (bits) {
    432   default:
    433     DEBUG(dbgs() << "unrecognized bit count of " << bits << '\n');
    434     break;
    435 
    436   case 32:
    437     switch (kind) {
    438     case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
    439       FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
    440       break;
    441     case llvm::MCSymbolRefExpr::VK_GOT:
    442       FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
    443                             : Hexagon::fixup_Hexagon_GOT_32;
    444       break;
    445     case llvm::MCSymbolRefExpr::VK_GOTOFF:
    446       FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
    447                             : Hexagon::fixup_Hexagon_GOTREL_32;
    448       break;
    449     case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
    450       FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
    451                             : Hexagon::fixup_Hexagon_GD_GOT_32;
    452       break;
    453     case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
    454       FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
    455                             : Hexagon::fixup_Hexagon_LD_GOT_32;
    456       break;
    457     case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
    458       FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
    459                             : Hexagon::fixup_Hexagon_IE_32;
    460       break;
    461     case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
    462       FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
    463                             : Hexagon::fixup_Hexagon_IE_GOT_32;
    464       break;
    465     case llvm::MCSymbolRefExpr::VK_TPREL:
    466       FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
    467                             : Hexagon::fixup_Hexagon_TPREL_32;
    468       break;
    469     case llvm::MCSymbolRefExpr::VK_DTPREL:
    470       FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
    471                             : Hexagon::fixup_Hexagon_DTPREL_32;
    472       break;
    473     default:
    474       FixupKind =
    475           *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
    476       break;
    477     }
    478     break;
    479 
    480   case 22:
    481     switch (kind) {
    482     case llvm::MCSymbolRefExpr::VK_Hexagon_GD_PLT:
    483       FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
    484       break;
    485     case llvm::MCSymbolRefExpr::VK_Hexagon_LD_PLT:
    486       FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
    487       break;
    488     default:
    489       if (MCID.isBranch() || MCID.isCall()) {
    490         FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
    491                               : Hexagon::fixup_Hexagon_B22_PCREL;
    492       } else {
    493         errs() << "unrecognized relocation, bits: " << bits << "\n";
    494         errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    495       }
    496       break;
    497     }
    498     break;
    499 
    500   case 16:
    501     if (*Extended) {
    502       switch (kind) {
    503       default:
    504         FixupKind = Hexagon::fixup_Hexagon_16_X;
    505         break;
    506       case llvm::MCSymbolRefExpr::VK_GOT:
    507         FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
    508         break;
    509       case llvm::MCSymbolRefExpr::VK_GOTOFF:
    510         FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
    511         break;
    512       case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
    513         FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
    514         break;
    515       case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
    516         FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
    517         break;
    518       case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
    519         FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
    520         break;
    521       case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
    522         FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
    523         break;
    524       case llvm::MCSymbolRefExpr::VK_TPREL:
    525         FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
    526         break;
    527       case llvm::MCSymbolRefExpr::VK_DTPREL:
    528         FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
    529         break;
    530       }
    531     } else
    532       switch (kind) {
    533       default:
    534         errs() << "unrecognized relocation, bits " << bits << "\n";
    535         errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    536         break;
    537       case llvm::MCSymbolRefExpr::VK_GOTOFF:
    538         if ((MCID.getOpcode() == Hexagon::HI) ||
    539             (MCID.getOpcode() == Hexagon::LO_H))
    540           FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
    541         else
    542           FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
    543         break;
    544       case llvm::MCSymbolRefExpr::VK_Hexagon_GPREL:
    545         FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
    546         break;
    547       case llvm::MCSymbolRefExpr::VK_Hexagon_LO16:
    548         FixupKind = Hexagon::fixup_Hexagon_LO16;
    549         break;
    550       case llvm::MCSymbolRefExpr::VK_Hexagon_HI16:
    551         FixupKind = Hexagon::fixup_Hexagon_HI16;
    552         break;
    553       case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
    554         FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
    555         break;
    556       case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
    557         FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
    558         break;
    559       case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
    560         FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
    561         break;
    562       case llvm::MCSymbolRefExpr::VK_TPREL:
    563         FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
    564         break;
    565       case llvm::MCSymbolRefExpr::VK_DTPREL:
    566         FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
    567         break;
    568       }
    569     break;
    570 
    571   case 15:
    572     if (MCID.isBranch() || MCID.isCall())
    573       FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
    574                             : Hexagon::fixup_Hexagon_B15_PCREL;
    575     break;
    576 
    577   case 13:
    578     if (MCID.isBranch())
    579       FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
    580     else {
    581       errs() << "unrecognized relocation, bits " << bits << "\n";
    582       errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    583     }
    584     break;
    585 
    586   case 12:
    587     if (*Extended)
    588       switch (kind) {
    589       default:
    590         FixupKind = Hexagon::fixup_Hexagon_12_X;
    591         break;
    592       // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
    593       case llvm::MCSymbolRefExpr::VK_GOT:
    594         FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
    595         break;
    596       case llvm::MCSymbolRefExpr::VK_GOTOFF:
    597         FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
    598         break;
    599       }
    600     else {
    601       errs() << "unrecognized relocation, bits " << bits << "\n";
    602       errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    603     }
    604     break;
    605 
    606   case 11:
    607     if (*Extended)
    608       switch (kind) {
    609       default:
    610         FixupKind = Hexagon::fixup_Hexagon_11_X;
    611         break;
    612       case llvm::MCSymbolRefExpr::VK_GOT:
    613         FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
    614         break;
    615       case llvm::MCSymbolRefExpr::VK_GOTOFF:
    616         FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
    617         break;
    618       case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
    619         FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
    620         break;
    621       case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
    622         FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
    623         break;
    624       case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
    625         FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
    626         break;
    627       case llvm::MCSymbolRefExpr::VK_TPREL:
    628         FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
    629         break;
    630       case llvm::MCSymbolRefExpr::VK_DTPREL:
    631         FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
    632         break;
    633       }
    634     else {
    635       errs() << "unrecognized relocation, bits " << bits << "\n";
    636       errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    637     }
    638     break;
    639 
    640   case 10:
    641     if (*Extended)
    642       FixupKind = Hexagon::fixup_Hexagon_10_X;
    643     break;
    644 
    645   case 9:
    646     if (MCID.isBranch() ||
    647         (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
    648       FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
    649                             : Hexagon::fixup_Hexagon_B9_PCREL;
    650     else if (*Extended)
    651       FixupKind = Hexagon::fixup_Hexagon_9_X;
    652     else {
    653       errs() << "unrecognized relocation, bits " << bits << "\n";
    654       errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    655     }
    656     break;
    657 
    658   case 8:
    659     if (*Extended)
    660       FixupKind = Hexagon::fixup_Hexagon_8_X;
    661     else {
    662       errs() << "unrecognized relocation, bits " << bits << "\n";
    663       errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    664     }
    665     break;
    666 
    667   case 7:
    668     if (MCID.isBranch() ||
    669         (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
    670       FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
    671                             : Hexagon::fixup_Hexagon_B7_PCREL;
    672     else if (*Extended)
    673       FixupKind = Hexagon::fixup_Hexagon_7_X;
    674     else {
    675       errs() << "unrecognized relocation, bits " << bits << "\n";
    676       errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    677     }
    678     break;
    679 
    680   case 6:
    681     if (*Extended) {
    682       switch (kind) {
    683       default:
    684         FixupKind = Hexagon::fixup_Hexagon_6_X;
    685         break;
    686       case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
    687         FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
    688         break;
    689       // This is part of an extender, GOT_11 is a
    690       // Word32_U6 unsigned/truncated reloc.
    691       case llvm::MCSymbolRefExpr::VK_GOT:
    692         FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
    693         break;
    694       case llvm::MCSymbolRefExpr::VK_GOTOFF:
    695         FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
    696         break;
    697       }
    698     } else {
    699       errs() << "unrecognized relocation, bits " << bits << "\n";
    700       errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
    701     }
    702     break;
    703 
    704   case 0:
    705     FixupKind = getFixupNoBits(MCII, MI, MO, kind);
    706     break;
    707   }
    708 
    709   MCExpr const *FixupExpression = (*Addend > 0 && isPCRel(FixupKind)) ?
    710     MCBinaryExpr::createAdd(MO.getExpr(),
    711                             MCConstantExpr::create(*Addend, MCT), MCT) :
    712     MO.getExpr();
    713 
    714   MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
    715                                   MCFixupKind(FixupKind), MI.getLoc());
    716   Fixups.push_back(fixup);
    717   // All of the information is in the fixup.
    718   return (0);
    719 }
    720 
    721 unsigned
    722 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
    723                                         SmallVectorImpl<MCFixup> &Fixups,
    724                                         MCSubtargetInfo const &STI) const {
    725   if (MO.isReg())
    726     return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
    727   if (MO.isImm())
    728     return static_cast<unsigned>(MO.getImm());
    729 
    730   // MO must be an ME.
    731   assert(MO.isExpr());
    732   return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
    733 }
    734 
    735 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
    736                                                 MCRegisterInfo const &MRI,
    737                                                 MCContext &MCT) {
    738   return new HexagonMCCodeEmitter(MII, MCT);
    739 }
    740 
    741 #include "HexagonGenMCCodeEmitter.inc"
    742