/external/llvm/lib/Target/ARM/ |
ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 45 MachineInstr *DefMI = LastMI; 59 DefMI = &*I; 63 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 65 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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MLxExpansionPass.cpp | 95 MachineInstr *DefMI = MRI->getVRegDef(Reg); 97 if (DefMI->getParent() != MBB) 99 if (DefMI->isCopyLike()) { 100 Reg = DefMI->getOperand(1).getReg(); 102 DefMI = MRI->getVRegDef(Reg); 105 } else if (DefMI->isInsertSubreg()) { 106 Reg = DefMI->getOperand(2).getReg(); 108 DefMI = MRI->getVRegDef(Reg); 114 return DefMI; 149 MachineInstr *DefMI = MRI->getVRegDef(Reg) [all...] |
ARMBaseInstrInfo.h | 278 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 285 const MachineInstr *DefMI, unsigned DefIdx, 341 const MachineInstr *DefMI, unsigned DefIdx, 345 const MachineInstr *DefMI,
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ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
TargetSchedule.cpp | 155 const MachineInstr *DefMI, unsigned DefOperIdx, 159 return TII->defaultDefLatency(SchedModel, DefMI); 164 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, 168 unsigned DefClass = DefMI->getDesc().getSchedClass(); 175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 183 TII->defaultDefLatency(SchedModel, DefMI)); 187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); 211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() 212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef( [all...] |
LiveRangeEdit.cpp | 52 const MachineInstr *DefMI, 54 assert(DefMI && "Missing instruction"); 56 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 66 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); 67 if (!DefMI) 69 checkRematerializable(VNI, DefMI, aa); 166 MachineInstr *DefMI = nullptr, *UseMI = nullptr; 172 if (DefMI && DefMI != MI) 176 DefMI = MI [all...] |
MachineTraceMetrics.cpp | 602 const MachineInstr *DefMI; 606 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) 607 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} 615 DefMI = DefI->getParent(); 761 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); 763 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; 766 unsigned Len = LIR.Height + Cycles[DefMI].Depth; 834 BlockInfo[Dep.DefMI->getParent()->getNumber()]; 839 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth [all...] |
InlineSpiller.cpp | 113 MachineInstr *DefMI; 124 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {} 127 bool hasDef() const { return DefByOrigPHI || DefMI; } 335 if (SVI.DefMI) 336 OS << " def: " << *SVI.DefMI; 399 DepSV.DefMI = SV.DefMI; 500 return SVI->second.DefMI; 621 SVI->second.DefMI = MI; 642 return SVI->second.DefMI; [all...] |
RegisterCoalescer.cpp | 654 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); 655 if (!DefMI) 657 if (!DefMI->isCommutable()) 659 // If DefMI is a two-address instruction then commuting it will change the 661 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 664 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 677 if (!TII->findCommutedOpIndices(DefMI, UseOpIdx, NewDstIdx)) 680 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 705 << *DefMI); 709 MachineBasicBlock *MBB = DefMI->getParent() [all...] |
TargetInstrInfo.cpp | [all...] |
MachineCSE.cpp | 133 MachineInstr *DefMI = MRI->getVRegDef(Reg); 134 if (!DefMI->isCopy()) 136 unsigned SrcReg = DefMI->getOperand(1).getReg(); 139 if (DefMI->getOperand(0).getSubReg()) 153 if (DefMI->getOperand(1).getSubReg()) 158 DEBUG(dbgs() << "Coalescing: " << *DefMI); 165 DefMI->eraseFromParent();
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PHIElimination.cpp | 158 for (MachineInstr *DefMI : ImpDefs) { 159 unsigned DefReg = DefMI->getOperand(0).getReg(); 162 LIS->RemoveMachineInstrFromMaps(DefMI); 163 DefMI->eraseFromParent(); 395 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 396 if (DefMI->isImplicitDef()) 397 ImpDefs.insert(DefMI);
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EarlyIfConversion.cpp | 245 MachineInstr *DefMI = MRI->getVRegDef(Reg); 246 if (!DefMI || DefMI->getParent() != Head) 248 if (InsertAfter.insert(DefMI).second) 249 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); 250 if (DefMI->isTerminator()) {
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TwoAddressInstructionPass.cpp | 318 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { 319 if (DefMI.getParent() != BB || DefMI.isDebugValue()) 322 Ret = &DefMI; 323 else if (Ret != &DefMI) 447 MachineInstr *DefMI = &MI; 453 if (!isPlainlyKilled(DefMI, Reg, LIS)) 462 DefMI = Begin->getParent(); 467 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) [all...] |
MachineSink.cpp | 174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 175 if (DefMI->isCopyLike()) 177 DEBUG(dbgs() << "Coalescing: " << *DefMI); 393 MachineInstr *DefMI = MRI->getVRegDef(Reg); 394 if (DefMI->getParent() == MI->getParent())
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/external/llvm/lib/Target/PowerPC/ |
PPCMIPeephole.cpp | 124 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); 128 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { 129 unsigned FeedImmed = DefMI->getOperand(3).getImm(); 131 = lookThruCopyLike(DefMI->getOperand(1).getReg()); 133 = lookThruCopyLike(DefMI->getOperand(2).getReg()); 154 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); 155 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); 167 .addOperand(DefMI->getOperand(1));
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PPCInstrInfo.h | 120 const MachineInstr *DefMI, unsigned DefIdx, 131 const MachineInstr *DefMI, 204 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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PPCVSXSwapRemoval.cpp | 614 MachineInstr* DefMI = MRI->getVRegDef(Reg); 615 assert(SwapMap.find(DefMI) != SwapMap.end() && 617 int DefIdx = SwapMap[DefMI]; 624 DEBUG(DefMI->dump()); 694 MachineInstr *DefMI = MRI->getVRegDef(UseReg); 695 int DefIdx = SwapMap[DefMI]; 705 DEBUG(DefMI->dump()); 750 MachineInstr *DefMI = MRI->getVRegDef(UseReg); 751 int DefIdx = SwapMap[DefMI]; 755 DEBUG(DefMI->dump()) [all...] |
/external/llvm/lib/Target/X86/ |
X86OptimizeLEAs.cpp | 132 for (auto DefMI : List) { 136 if (!isSimilarMemOp(MI, MemOpNo, *DefMI, 1, AddrDispShiftTemp)) 149 MRI->getRegClass(DefMI->getOperand(0).getReg())) 156 int DistTemp = calcInstrDist(*DefMI, MI); 166 LEA = DefMI; 258 MachineInstr *DefMI; 261 if (!chooseBestLEA(List, MI, DefMI, AddrDispShift, Dist)) 271 DefMI->removeFromParent(); 272 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); 276 MRI->clearKillFlags(DefMI->getOperand(0).getReg()) [all...] |
X86CallFrameOptimization.cpp | 543 MachineBasicBlock::iterator DefMI = MRI->getVRegDef(Reg); 547 if (DefMI->getOpcode() != X86::MOV32rm || 548 DefMI->getParent() != FrameSetup->getParent()) 551 // Make sure we don't have any instructions between DefMI and the 553 for (auto I = DefMI; I != FrameSetup; ++I) 557 return DefMI;
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/external/llvm/lib/Target/Mips/ |
MipsOptimizePICCall.cpp | 261 MachineInstr *DefMI = MRI.getVRegDef(Reg); 263 assert(DefMI); 265 // See if DefMI is an instruction that loads from a GOT entry that holds the 267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) 270 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); 276 assert(DefMI->hasOneMemOperand()); 277 Val = (*DefMI->memoperands_begin())->getValue(); 279 Val = (*DefMI->memoperands_begin())->getPseudoValue();
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/external/llvm/include/llvm/CodeGen/ |
TargetSchedule.h | 162 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 184 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
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MachineTraceMetrics.h | 292 /// is part of the trace of the user instruction. It is assumed that DefMI 294 bool isDepInTrace(const MachineInstr *DefMI, 314 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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LiveRangeEdit.h | 171 /// values if DefMI may be rematerializable. 172 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | [all...] |