| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.h | 50 struct ExtType {
54 ExtType() : Type(0), Width(0) {}
55 ExtType(char t, uint16_t w) : Type(t), Width(w) {}
58 typedef DenseMap<unsigned, ExtType> RegExtMap;
|
| HexagonBitTracker.cpp | 71 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
[all...] |
| HexagonISelDAGToDAG.cpp | 380 ISD::LoadExtType ExtType = LD->getExtensionType();
381 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
429 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| evntcons.h | 41 USHORT ExtType;
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 590 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
595 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
597 return LoadExtActions[ValI][MemI][ExtType];
601 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
603 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
608 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
610 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
611 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 203 ISD::LoadExtType ExtType = LD->getExtensionType();
204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
500 ISD::LoadExtType ExtType = LD->getExtensionType();
597 switch (ExtType) {
620 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 473 ISD::LoadExtType ExtType =
476 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
[all...] |
| SelectionDAG.cpp | 230 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {
231 switch (ExtType) {
[all...] |
| DAGCombiner.cpp | 216 ISD::NodeType ExtType);
[all...] |
| LegalizeTypes.h | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.h | 133 ISD::LoadExtType ExtType,
|
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 55 AArch64_AM::ShiftExtendType ExtType;
66 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
70 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
71 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
175 AArch64_AM::ShiftExtendType ExtType,
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
