Home | History | Annotate | Download | only in AMDGPU 
      1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 /// \file
     11 /// \brief Interface definition of the TargetLowering class that is common
     12 /// to all AMD GPUs.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
     17 #define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
     18 
     19 #include "llvm/Target/TargetLowering.h"
     20 
     21 namespace llvm {
     22 
     23 class AMDGPUMachineFunction;
     24 class AMDGPUSubtarget;
     25 class MachineRegisterInfo;
     26 
     27 class AMDGPUTargetLowering : public TargetLowering {
     28 protected:
     29   const AMDGPUSubtarget *Subtarget;
     30 
     31 private:
     32   SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
     33                                    const SDValue &InitPtr,
     34                                    SDValue Chain,
     35                                    SelectionDAG &DAG) const;
     36   SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
     37   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
     38   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
     39   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
     40   /// \brief Lower vector stores by merging the vector elements into an integer
     41   /// of the same bitwidth.
     42   SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
     43   /// \brief Split a vector store into multiple scalar stores.
     44   /// \returns The resulting chain.
     45 
     46   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
     47   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
     48   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
     49   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
     50   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
     51 
     52   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
     53   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
     54   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
     55   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
     56 
     57   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
     58   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
     59   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
     60 
     61   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
     62   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
     63   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
     64 
     65   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
     66 
     67   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
     68   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
     69   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
     70 
     71 protected:
     72   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
     73   static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
     74 
     75   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
     76                                      SelectionDAG &DAG) const;
     77 
     78   /// \brief Split a vector load into a scalar load of each component.
     79   SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
     80 
     81   /// \brief Split a vector load into 2 loads of half the vector.
     82   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
     83 
     84   /// \brief Split a vector store into a scalar store of each component.
     85   SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
     86 
     87   /// \brief Split a vector store into 2 stores of half the vector.
     88   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
     89 
     90   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
     91   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
     92   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
     93   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
     94   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
     95   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
     96                                     SmallVectorImpl<SDValue> &Results) const;
     97   bool isHWTrueValue(SDValue Op) const;
     98   bool isHWFalseValue(SDValue Op) const;
     99 
    100   /// The SelectionDAGBuilder will automatically promote function arguments
    101   /// with illegal types.  However, this does not work for the AMDGPU targets
    102   /// since the function arguments are stored in memory as these illegal types.
    103   /// In order to handle this properly we need to get the origianl types sizes
    104   /// from the LLVM IR Function and fixup the ISD:InputArg values before
    105   /// passing them to AnalyzeFormalArguments()
    106   void getOriginalFunctionArgs(SelectionDAG &DAG,
    107                                const Function *F,
    108                                const SmallVectorImpl<ISD::InputArg> &Ins,
    109                                SmallVectorImpl<ISD::InputArg> &OrigIns) const;
    110   void AnalyzeFormalArguments(CCState &State,
    111                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
    112 
    113 public:
    114   AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
    115 
    116   bool isFAbsFree(EVT VT) const override;
    117   bool isFNegFree(EVT VT) const override;
    118   bool isTruncateFree(EVT Src, EVT Dest) const override;
    119   bool isTruncateFree(Type *Src, Type *Dest) const override;
    120 
    121   bool isZExtFree(Type *Src, Type *Dest) const override;
    122   bool isZExtFree(EVT Src, EVT Dest) const override;
    123   bool isZExtFree(SDValue Val, EVT VT2) const override;
    124 
    125   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
    126 
    127   MVT getVectorIdxTy(const DataLayout &) const override;
    128   bool isSelectSupported(SelectSupportKind) const override;
    129 
    130   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
    131   bool ShouldShrinkFPConstant(EVT VT) const override;
    132   bool shouldReduceLoadWidth(SDNode *Load,
    133                              ISD::LoadExtType ExtType,
    134                              EVT ExtVT) const override;
    135 
    136   bool isLoadBitCastBeneficial(EVT, EVT) const override;
    137 
    138   bool storeOfVectorConstantIsCheap(EVT MemVT,
    139                                     unsigned NumElem,
    140                                     unsigned AS) const override;
    141   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
    142   bool isCheapToSpeculateCttz() const override;
    143   bool isCheapToSpeculateCtlz() const override;
    144 
    145   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
    146                       bool isVarArg,
    147                       const SmallVectorImpl<ISD::OutputArg> &Outs,
    148                       const SmallVectorImpl<SDValue> &OutVals,
    149                       SDLoc DL, SelectionDAG &DAG) const override;
    150   SDValue LowerCall(CallLoweringInfo &CLI,
    151                     SmallVectorImpl<SDValue> &InVals) const override;
    152 
    153   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
    154                                   SelectionDAG &DAG) const;
    155 
    156   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
    157   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
    158   void ReplaceNodeResults(SDNode * N,
    159                           SmallVectorImpl<SDValue> &Results,
    160                           SelectionDAG &DAG) const override;
    161 
    162   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
    163   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
    164   SDValue CombineFMinMaxLegacy(SDLoc DL,
    165                                EVT VT,
    166                                SDValue LHS,
    167                                SDValue RHS,
    168                                SDValue True,
    169                                SDValue False,
    170                                SDValue CC,
    171                                DAGCombinerInfo &DCI) const;
    172 
    173   const char* getTargetNodeName(unsigned Opcode) const override;
    174 
    175   SDValue getRsqrtEstimate(SDValue Operand,
    176                            DAGCombinerInfo &DCI,
    177                            unsigned &RefinementSteps,
    178                            bool &UseOneConstNR) const override;
    179   SDValue getRecipEstimate(SDValue Operand,
    180                            DAGCombinerInfo &DCI,
    181                            unsigned &RefinementSteps) const override;
    182 
    183   virtual SDNode *PostISelFolding(MachineSDNode *N,
    184                                   SelectionDAG &DAG) const {
    185     return N;
    186   }
    187 
    188   /// \brief Determine which of the bits specified in \p Mask are known to be
    189   /// either zero or one and return them in the \p KnownZero and \p KnownOne
    190   /// bitsets.
    191   void computeKnownBitsForTargetNode(const SDValue Op,
    192                                      APInt &KnownZero,
    193                                      APInt &KnownOne,
    194                                      const SelectionDAG &DAG,
    195                                      unsigned Depth = 0) const override;
    196 
    197   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
    198                                            unsigned Depth = 0) const override;
    199 
    200   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
    201   /// MachineFunction.
    202   ///
    203   /// \returns a RegisterSDNode representing Reg.
    204   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
    205                                        const TargetRegisterClass *RC,
    206                                        unsigned Reg, EVT VT) const;
    207 
    208   enum ImplicitParameter {
    209     GRID_DIM,
    210     GRID_OFFSET
    211   };
    212 
    213   /// \brief Helper function that returns the byte offset of the given
    214   /// type of implicit parameter.
    215   uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI,
    216                                       const ImplicitParameter Param) const;
    217 };
    218 
    219 namespace AMDGPUISD {
    220 
    221 enum NodeType : unsigned {
    222   // AMDIL ISD Opcodes
    223   FIRST_NUMBER = ISD::BUILTIN_OP_END,
    224   CALL,        // Function call based on a single integer
    225   UMUL,        // 32bit unsigned multiplication
    226   RET_FLAG,
    227   BRANCH_COND,
    228   // End AMDIL ISD Opcodes
    229   DWORDADDR,
    230   FRACT,
    231   CLAMP,
    232 
    233   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
    234   // Denormals handled on some parts.
    235   COS_HW,
    236   SIN_HW,
    237   FMAX_LEGACY,
    238   FMIN_LEGACY,
    239   FMAX3,
    240   SMAX3,
    241   UMAX3,
    242   FMIN3,
    243   SMIN3,
    244   UMIN3,
    245   URECIP,
    246   DIV_SCALE,
    247   DIV_FMAS,
    248   DIV_FIXUP,
    249   TRIG_PREOP, // 1 ULP max error for f64
    250 
    251   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
    252   //            For f64, max error 2^29 ULP, handles denormals.
    253   RCP,
    254   RSQ,
    255   RSQ_LEGACY,
    256   RSQ_CLAMPED,
    257   LDEXP,
    258   FP_CLASS,
    259   DOT4,
    260   CARRY,
    261   BORROW,
    262   BFE_U32, // Extract range of bits with zero extension to 32-bits.
    263   BFE_I32, // Extract range of bits with sign extension to 32-bits.
    264   BFI, // (src0 & src1) | (~src0 & src2)
    265   BFM, // Insert a range of bits into a 32-bit word.
    266   MUL_U24,
    267   MUL_I24,
    268   MAD_U24,
    269   MAD_I24,
    270   TEXTURE_FETCH,
    271   EXPORT,
    272   CONST_ADDRESS,
    273   REGISTER_LOAD,
    274   REGISTER_STORE,
    275   LOAD_INPUT,
    276   SAMPLE,
    277   SAMPLEB,
    278   SAMPLED,
    279   SAMPLEL,
    280 
    281   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
    282   CVT_F32_UBYTE0,
    283   CVT_F32_UBYTE1,
    284   CVT_F32_UBYTE2,
    285   CVT_F32_UBYTE3,
    286   /// This node is for VLIW targets and it is used to represent a vector
    287   /// that is stored in consecutive registers with the same channel.
    288   /// For example:
    289   ///   |X  |Y|Z|W|
    290   /// T0|v.x| | | |
    291   /// T1|v.y| | | |
    292   /// T2|v.z| | | |
    293   /// T3|v.w| | | |
    294   BUILD_VERTICAL_VECTOR,
    295   /// Pointer to the start of the shader's constant data.
    296   CONST_DATA_PTR,
    297   SENDMSG,
    298   INTERP_MOV,
    299   INTERP_P1,
    300   INTERP_P2,
    301   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
    302   STORE_MSKOR,
    303   LOAD_CONSTANT,
    304   TBUFFER_STORE_FORMAT,
    305   LAST_AMDGPU_ISD_NUMBER
    306 };
    307 
    308 
    309 } // End namespace AMDGPUISD
    310 
    311 } // End namespace llvm
    312 
    313 #endif
    314