| /prebuilts/go/darwin-x86/src/math/ |
| sin_386.s | 31 FSIN // F0=sin(x) if -2**63 < x < 2**63
45 FSIN // F0=sin(reduced_x)
|
| /prebuilts/go/linux-x86/src/math/ |
| sin_386.s | 31 FSIN // F0=sin(x) if -2**63 < x < 2**63
45 FSIN // F0=sin(reduced_x)
|
| /ndk/sources/host-tools/nawk-20071023/ |
| awk.h | 123 #define FSIN 9
|
| lex.c | 79 { "sin", FSIN, BLTIN },
|
| run.c | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 511 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
515 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
528 /// FSINCOS - Compute both fsin and fcos as a single operation.
[all...] |
| BasicTTIImpl.h | 621 ISD = ISD::FSIN;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 159 case ISD::FSIN: return "fsin";
|
| LegalizeVectorOps.cpp | 308 case ISD::FSIN:
[all...] |
| LegalizeFloatTypes.cpp | 102 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break;
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 93 case ISD::FSIN:
649 case ISD::FSIN:
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 135 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW,
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 65 setOperationAction(ISD::FSIN, MVT::f32, Custom);
600 case ISD::FSIN: return LowerTrig(Op, DAG);
[all...] |
| SIISelLowering.cpp | 80 setOperationAction(ISD::FSIN, MVT::f32, Custom);
[all...] |
| AMDGPUISelLowering.cpp | 359 setOperationAction(ISD::FSIN, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 160 setOperationAction(ISD::FSIN, MVT::f128, Expand);
265 setOperationAction(ISD::FSIN, MVT::f32, Expand);
266 setOperationAction(ISD::FSIN, MVT::f64, Expand);
295 setOperationAction(ISD::FSIN, MVT::f16, Promote);
341 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
373 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
545 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
648 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 359 setOperationAction(ISD::FSIN, MVT::f32, Expand);
360 setOperationAction(ISD::FSIN, MVT::f64, Expand);
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 502 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
520 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
537 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
661 setOperationAction(ISD::FSIN, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 161 setOperationAction(ISD::FSIN , MVT::f64, Expand);
167 setOperationAction(ISD::FSIN , MVT::f32, Expand);
461 setOperationAction(ISD::FSIN, VT, Expand);
695 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
741 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 547 setOperationAction(ISD::FSIN , MVT::f64, Expand);
550 setOperationAction(ISD::FSIN , MVT::f32, Expand);
577 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FSIN , MVT::f64, Expand);
605 setOperationAction(ISD::FSIN , MVT::f64, Expand);
606 setOperationAction(ISD::FSIN , MVT::f32, Expand);
655 setOperationAction(ISD::FSIN , MVT::f80, Expand);
704 setOperationAction(ISD::FSIN, VT, Expand);
[all...] |
