/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 9 // The Hexagon processor has no instructions that load or store predicate 20 #include "Hexagon.h" 60 return "Hexagon Expand Predicate Spill Code"; 83 if (Opc == Hexagon::S2_storerb_pci_pseudo || 84 Opc == Hexagon::S2_storerh_pci_pseudo || 85 Opc == Hexagon::S2_storeri_pci_pseudo || 86 Opc == Hexagon::S2_storerd_pci_pseudo || 87 Opc == Hexagon::S2_storerf_pci_pseudo) { 89 if (Opc == Hexagon::S2_storerd_pci_pseudo) 90 Opcode = Hexagon::S2_storerd_pci [all...] |
HexagonRegisterInfo.cpp | 1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===// 10 // This file contains the Hexagon implementation of the TargetRegisterInfo 16 #include "Hexagon.h" 43 : HexagonGenRegisterInfo(Hexagon::R31) {} 47 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || 48 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1 [all...] |
HexagonInstrInfo.cpp | 1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===// 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 15 #include "Hexagon.h" 34 #define DEBUG_TYPE "hexagon-instrinfo" 43 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, 47 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction", 50 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule", 70 /// Constants for Hexagon instructions. 103 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP) [all...] |
HexagonFrameLowering.h | 1 //=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=// 13 #include "Hexagon.h" 61 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, 62 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, 63 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 } [all...] |
HexagonNewValueJump.cpp | 1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===// 10 // This implements NewValueJump pass in Hexagon. 25 #include "Hexagon.h" 50 #define DEBUG_TYPE "hexagon-nvj" 86 return "Hexagon NewValueJump"; 102 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj", 103 "Hexagon NewValueJump", false, false) 105 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj", 106 "Hexagon NewValueJump", false, false) 182 if (MII->getOpcode() == Hexagon::J2_call [all...] |
HexagonAsmPrinter.cpp | 1 //===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===// 11 // of machine-dependent LLVM code to Hexagon assembly language. This printer is 16 #include "Hexagon.h" 69 "hexagon-align-calls", cl::Hidden, cl::init(true), 70 cl::desc("Insert falign after call instruction for Hexagon target")); 75 assert(Hexagon::IntRegsRegClass.contains(Reg)); 78 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); 144 // Hexagon never has a prefix. 268 case Hexagon::CONST64_Float_Real: 269 case Hexagon::CONST64_Int_Real [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCCodeEmitter.cpp | 1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===// 10 #include "Hexagon.h" 31 using namespace Hexagon; 101 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10, 102 Hexagon::R11, Hexagon::R12, Hexagon::R13, 103 Hexagon::R14, Hexagon::R15} [all...] |
HexagonMCDuplexInfo.cpp | 24 using namespace Hexagon; 26 #define DEBUG_TYPE "hexagon-mcduplex-info" 191 case Hexagon::L2_loadri_io: 198 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { 208 case Hexagon::L2_loadrub_io: 228 case Hexagon::L2_loadrh_io: 229 case Hexagon::L2_loadruh_io: 239 case Hexagon::L2_loadrb_io: 249 case Hexagon::L2_loadrd_io: 254 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg & [all...] |
HexagonMCCompound.cpp | 2 //=== HexagonMCCompound.cpp - Hexagon Compound checker -------===// 14 #include "Hexagon.h" 28 using namespace Hexagon; 30 #define DEBUG_TYPE "hexagon-mccompound" 95 case Hexagon::C2_cmpeq: 96 case Hexagon::C2_cmpgt: 97 case Hexagon::C2_cmpgtu: 103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && 108 case Hexagon::C2_cmpeqi [all...] |
/external/llvm/lib/Target/Hexagon/Disassembler/ |
HexagonDisassembler.cpp | 1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 10 #define DEBUG_TYPE "hexagon-disassembler" 12 #include "Hexagon.h" 36 using namespace Hexagon; 41 /// \brief Hexagon disassembler for all Hexagon platforms. 284 MI.setOpcode(Hexagon::DuplexIClass0); 305 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 323 MI.getOpcode() == Hexagon::A4_ext) { 337 unsigned reg = i->getReg() - Hexagon::R0 [all...] |
/external/llvm/test/MC/Hexagon/instructions/ |
memop.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.6 MEMOP
|
nv_j.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.7.1 NV/J
|
alu32_alu.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
|
alu32_perm.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
|
alu32_pred.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.1.3 ALU32/PRED
|
cr.s | 1 # RUN: llvm-mc --triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.2 CR
|
j.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.4 J
|
jr.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.3 JR
|
ld.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.5 LD
|
nv_st.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.7.2 NV/ST
|
st.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.8 ST
|
system_user.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER
|
xtype_alu.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU
|
xtype_bit.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.10.2 XTYPE/BIT
|
xtype_complex.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s 2 # Hexagon Programmer's Reference Manual 11.10.3 XTYPE/COMPLEX
|