| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 113 int64_t imms = Op3.getImm(); local
114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
116 shift = 31 - imms;
117 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
118 ((imms + 1 == immr))) {
120 shift = 63 - imms;
121 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
124 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
127 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | [all...] |
| disasm-arm64.cc | 421 unsigned s = instr->ImmS();
[all...] |
| assembler-arm64-inl.h | 1039 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
1040 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1041 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1043 return imms << ImmS_offset;
1056 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
1058 DCHECK(is_uint6(imms));
1059 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
1061 return imms << ImmSetBits_offset;
[all...] |
| constants-arm64.h | 161 V_(ImmS, 15, 10, Bits) \
[all...] |
| assembler-arm64.h | [all...] |
| simulator-arm64.cc | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.cc | 1090 unsigned imms) {
1094 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1101 unsigned imms) {
1105 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1112 unsigned imms) {
1116 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1127 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.size()) | Rn(rn) | Rd(rd))
[all...] |
| constants-a64.h | 87 V_(ImmS, 15, 10, Bits) \
[all...] |
| disasm-a64.cc | 434 unsigned s = instr->ImmS();
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.h | [all...] |
