| /external/valgrind/none/tests/mips64/ |
| logical_instructions.c | 6 AND=0, ANDI, LUI, NOR,
52 case NOR:
54 TEST1("nor $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
56 TEST1("nor $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/ |
| list-insns.s | 217 NOR $32,$170,$151
218 NOR $182,$20,245
|
| list-insns.l | 232 217 0348 C420AA97 NOR \$32,\$170,\$151
233 218 034c C5B614F5 NOR \$182,\$20,245
|
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_32.c | 121 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG));
123 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | D(dst), DR(dst)));
159 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG));
238 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG));
|
| sljitNativeMIPS_64.c | 213 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG));
215 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | D(dst), DR(dst)));
251 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG));
330 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(OVERFLOW_FLAG), OVERFLOW_FLAG));
|
| sljitNativePPC_32.c | 87 return push_inst(compiler, NOR | RC(flags) | S(src2) | A(dst) | B(src2));
|
| sljitNativePPC_64.c | 203 return push_inst(compiler, NOR | RC(flags) | S(src2) | A(dst) | B(src2));
|
| sljitNativeTILEGX_64.c | 400 #define NOR(dst, srca, srcb) \
[all...] |
| sljitNativeMIPS_common.c | 157 #define NOR (HI(0) | LO(39))
[all...] |
| sljitNativePPC_common.c | 193 #define NOR (HI(31) | LO(124))
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 326 case Mips::NOR:
328 // nor $r0, $r1, $zero => not $r0, $r1
331 // nor $r0, $r1, $zero => not $r0, $r1
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 527 mMips->NOR(Rd, Op2, 0); // NOT is NOR with 0
555 mMips->NOR(Rd, Rd, 0); // NOT is NOR with 0
[all...] |
| MIPSAssembler.h | 309 void NOR(int Rd, int Rs, int Rt);
|
| MIPS64Assembler.cpp | 523 mMips->NOR(Rd, Op2, 0); // NOT is NOR with 0
546 mMips->NOR(Rd, Rd, 0); // NOT is NOR with 0
[all...] |
| /external/selinux/policycoreutils/mcstrans/share/examples/nato/setrans.d/ |
| eyes-only.conf | 493 ~c366=NOR # Norway
|
| rel.conf | 499 ~c200,~c366=NOR # Norway
|
| /external/v8/src/mips/ |
| constants-mips.h | 444 NOR = ((4U << 3) + 7),
937 FunctionFieldToBitNumber(XOR) | FunctionFieldToBitNumber(NOR) |
[all...] |
| assembler-mips.cc | 1706 void Assembler::nor(Register rd, Register rs, Register rt) { function in class:v8::Assembler
[all...] |
| simulator-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 437 NOR = ((4U << 3) + 7),
982 FunctionFieldToBitNumber(XOR) | FunctionFieldToBitNumber(NOR) |
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| nios2r1.h | 411 #define MATCH_R1_NOR MATCH_R1_OPX0 (NOR)
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| nds32-dis.c | 553 case ALU1 (NOR):
|
| /external/opencv3/modules/core/src/ |
| gl_core_3_1.hpp | 365 NOR = 0x1508,
[all...] |
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
| org.sat4j.core_2.2.0.v20100429.jar | |
