1 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_MIPS_CONSTANTS_H_ 6 #define V8_MIPS_CONSTANTS_H_ 7 #include "src/globals.h" 8 // UNIMPLEMENTED_ macro for MIPS. 9 #ifdef DEBUG 10 #define UNIMPLEMENTED_MIPS() \ 11 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \ 12 __FILE__, __LINE__, __func__) 13 #else 14 #define UNIMPLEMENTED_MIPS() 15 #endif 16 17 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n") 18 19 enum ArchVariants { 20 kMips32r1 = v8::internal::MIPSr1, 21 kMips32r2 = v8::internal::MIPSr2, 22 kMips32r6 = v8::internal::MIPSr6, 23 kLoongson 24 }; 25 26 #ifdef _MIPS_ARCH_MIPS32R2 27 static const ArchVariants kArchVariant = kMips32r2; 28 #elif _MIPS_ARCH_MIPS32R6 29 static const ArchVariants kArchVariant = kMips32r6; 30 #elif _MIPS_ARCH_LOONGSON 31 // The loongson flag refers to the LOONGSON architectures based on MIPS-III, 32 // which predates (and is a subset of) the mips32r2 and r1 architectures. 33 static const ArchVariants kArchVariant = kLoongson; 34 #elif _MIPS_ARCH_MIPS32RX 35 // This flags referred to compatibility mode that creates universal code that 36 // can run on any MIPS32 architecture revision. The dynamically generated code 37 // by v8 is specialized for the MIPS host detected in runtime probing. 38 static const ArchVariants kArchVariant = kMips32r1; 39 #else 40 static const ArchVariants kArchVariant = kMips32r1; 41 #endif 42 43 enum Endianness { 44 kLittle, 45 kBig 46 }; 47 48 #if defined(V8_TARGET_LITTLE_ENDIAN) 49 static const Endianness kArchEndian = kLittle; 50 #elif defined(V8_TARGET_BIG_ENDIAN) 51 static const Endianness kArchEndian = kBig; 52 #else 53 #error Unknown endianness 54 #endif 55 56 enum FpuMode { 57 kFP32, 58 kFP64, 59 kFPXX 60 }; 61 62 #if defined(FPU_MODE_FP32) 63 static const FpuMode kFpuMode = kFP32; 64 #elif defined(FPU_MODE_FP64) 65 static const FpuMode kFpuMode = kFP64; 66 #elif defined(FPU_MODE_FPXX) 67 #if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS32R6) 68 static const FpuMode kFpuMode = kFPXX; 69 #else 70 #error "FPXX is supported only on Mips32R2 and Mips32R6" 71 #endif 72 #else 73 static const FpuMode kFpuMode = kFP32; 74 #endif 75 76 #if(defined(__mips_hard_float) && __mips_hard_float != 0) 77 // Use floating-point coprocessor instructions. This flag is raised when 78 // -mhard-float is passed to the compiler. 79 const bool IsMipsSoftFloatABI = false; 80 #elif(defined(__mips_soft_float) && __mips_soft_float != 0) 81 // This flag is raised when -msoft-float is passed to the compiler. 82 // Although FPU is a base requirement for v8, soft-float ABI is used 83 // on soft-float systems with FPU kernel emulation. 84 const bool IsMipsSoftFloatABI = true; 85 #else 86 const bool IsMipsSoftFloatABI = true; 87 #endif 88 89 #if defined(V8_TARGET_LITTLE_ENDIAN) 90 const uint32_t kHoleNanUpper32Offset = 4; 91 const uint32_t kHoleNanLower32Offset = 0; 92 #elif defined(V8_TARGET_BIG_ENDIAN) 93 const uint32_t kHoleNanUpper32Offset = 0; 94 const uint32_t kHoleNanLower32Offset = 4; 95 #else 96 #error Unknown endianness 97 #endif 98 99 #define IsFp64Mode() (kFpuMode == kFP64) 100 #define IsFp32Mode() (kFpuMode == kFP32) 101 #define IsFpxxMode() (kFpuMode == kFPXX) 102 103 #ifndef _MIPS_ARCH_MIPS32RX 104 #define IsMipsArchVariant(check) \ 105 (kArchVariant == check) 106 #else 107 #define IsMipsArchVariant(check) \ 108 (CpuFeatures::IsSupported(static_cast<CpuFeature>(check))) 109 #endif 110 111 #if defined(V8_TARGET_LITTLE_ENDIAN) 112 const uint32_t kMipsLwrOffset = 0; 113 const uint32_t kMipsLwlOffset = 3; 114 const uint32_t kMipsSwrOffset = 0; 115 const uint32_t kMipsSwlOffset = 3; 116 #elif defined(V8_TARGET_BIG_ENDIAN) 117 const uint32_t kMipsLwrOffset = 3; 118 const uint32_t kMipsLwlOffset = 0; 119 const uint32_t kMipsSwrOffset = 3; 120 const uint32_t kMipsSwlOffset = 0; 121 #else 122 #error Unknown endianness 123 #endif 124 125 #define __STDC_FORMAT_MACROS 126 #include <inttypes.h> 127 128 // Defines constants and accessor classes to assemble, disassemble and 129 // simulate MIPS32 instructions. 130 // 131 // See: MIPS32 Architecture For Programmers 132 // Volume II: The MIPS32 Instruction Set 133 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf. 134 135 namespace v8 { 136 namespace internal { 137 138 // ----------------------------------------------------------------------------- 139 // Registers and FPURegisters. 140 141 // Number of general purpose registers. 142 const int kNumRegisters = 32; 143 const int kInvalidRegister = -1; 144 145 // Number of registers with HI, LO, and pc. 146 const int kNumSimuRegisters = 35; 147 148 // In the simulator, the PC register is simulated as the 34th register. 149 const int kPCRegister = 34; 150 151 // Number coprocessor registers. 152 const int kNumFPURegisters = 32; 153 const int kInvalidFPURegister = -1; 154 155 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented. 156 const int kFCSRRegister = 31; 157 const int kInvalidFPUControlRegister = -1; 158 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1; 159 const int32_t kFPUInvalidResultNegative = static_cast<int32_t>(1 << 31); 160 const uint64_t kFPU64InvalidResult = 161 static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1; 162 const int64_t kFPU64InvalidResultNegative = 163 static_cast<int64_t>(static_cast<uint64_t>(1) << 63); 164 165 // FCSR constants. 166 const uint32_t kFCSRInexactFlagBit = 2; 167 const uint32_t kFCSRUnderflowFlagBit = 3; 168 const uint32_t kFCSROverflowFlagBit = 4; 169 const uint32_t kFCSRDivideByZeroFlagBit = 5; 170 const uint32_t kFCSRInvalidOpFlagBit = 6; 171 const uint32_t kFCSRNaN2008FlagBit = 18; 172 173 const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit; 174 const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit; 175 const uint32_t kFCSROverflowFlagMask = 1 << kFCSROverflowFlagBit; 176 const uint32_t kFCSRDivideByZeroFlagMask = 1 << kFCSRDivideByZeroFlagBit; 177 const uint32_t kFCSRInvalidOpFlagMask = 1 << kFCSRInvalidOpFlagBit; 178 const uint32_t kFCSRNaN2008FlagMask = 1 << kFCSRNaN2008FlagBit; 179 180 const uint32_t kFCSRFlagMask = 181 kFCSRInexactFlagMask | 182 kFCSRUnderflowFlagMask | 183 kFCSROverflowFlagMask | 184 kFCSRDivideByZeroFlagMask | 185 kFCSRInvalidOpFlagMask; 186 187 const uint32_t kFCSRExceptionFlagMask = kFCSRFlagMask ^ kFCSRInexactFlagMask; 188 189 // 'pref' instruction hints 190 const int32_t kPrefHintLoad = 0; 191 const int32_t kPrefHintStore = 1; 192 const int32_t kPrefHintLoadStreamed = 4; 193 const int32_t kPrefHintStoreStreamed = 5; 194 const int32_t kPrefHintLoadRetained = 6; 195 const int32_t kPrefHintStoreRetained = 7; 196 const int32_t kPrefHintWritebackInvalidate = 25; 197 const int32_t kPrefHintPrepareForStore = 30; 198 199 // Helper functions for converting between register numbers and names. 200 class Registers { 201 public: 202 // Return the name of the register. 203 static const char* Name(int reg); 204 205 // Lookup the register number for the name provided. 206 static int Number(const char* name); 207 208 struct RegisterAlias { 209 int reg; 210 const char* name; 211 }; 212 213 static const int32_t kMaxValue = 0x7fffffff; 214 static const int32_t kMinValue = 0x80000000; 215 216 private: 217 static const char* names_[kNumSimuRegisters]; 218 static const RegisterAlias aliases_[]; 219 }; 220 221 // Helper functions for converting between register numbers and names. 222 class FPURegisters { 223 public: 224 // Return the name of the register. 225 static const char* Name(int reg); 226 227 // Lookup the register number for the name provided. 228 static int Number(const char* name); 229 230 struct RegisterAlias { 231 int creg; 232 const char* name; 233 }; 234 235 private: 236 static const char* names_[kNumFPURegisters]; 237 static const RegisterAlias aliases_[]; 238 }; 239 240 241 // ----------------------------------------------------------------------------- 242 // Instructions encoding constants. 243 244 // On MIPS all instructions are 32 bits. 245 typedef int32_t Instr; 246 247 // Special Software Interrupt codes when used in the presence of the MIPS 248 // simulator. 249 enum SoftwareInterruptCodes { 250 // Transition to C code. 251 call_rt_redirected = 0xfffff 252 }; 253 254 // On MIPS Simulator breakpoints can have different codes: 255 // - Breaks between 0 and kMaxWatchpointCode are treated as simple watchpoints, 256 // the simulator will run through them and print the registers. 257 // - Breaks between kMaxWatchpointCode and kMaxStopCode are treated as stop() 258 // instructions (see Assembler::stop()). 259 // - Breaks larger than kMaxStopCode are simple breaks, dropping you into the 260 // debugger. 261 const uint32_t kMaxWatchpointCode = 31; 262 const uint32_t kMaxStopCode = 127; 263 STATIC_ASSERT(kMaxWatchpointCode < kMaxStopCode); 264 265 266 // ----- Fields offset and length. 267 const int kOpcodeShift = 26; 268 const int kOpcodeBits = 6; 269 const int kRsShift = 21; 270 const int kRsBits = 5; 271 const int kRtShift = 16; 272 const int kRtBits = 5; 273 const int kRdShift = 11; 274 const int kRdBits = 5; 275 const int kSaShift = 6; 276 const int kSaBits = 5; 277 const int kLsaSaBits = 2; 278 const int kFunctionShift = 0; 279 const int kFunctionBits = 6; 280 const int kLuiShift = 16; 281 const int kBp2Shift = 6; 282 const int kBp2Bits = 2; 283 284 const int kImm16Shift = 0; 285 const int kImm16Bits = 16; 286 const int kImm18Shift = 0; 287 const int kImm18Bits = 18; 288 const int kImm19Shift = 0; 289 const int kImm19Bits = 19; 290 const int kImm21Shift = 0; 291 const int kImm21Bits = 21; 292 const int kImm26Shift = 0; 293 const int kImm26Bits = 26; 294 const int kImm28Shift = 0; 295 const int kImm28Bits = 28; 296 const int kImm32Shift = 0; 297 const int kImm32Bits = 32; 298 299 // In branches and jumps immediate fields point to words, not bytes, 300 // and are therefore shifted by 2. 301 const int kImmFieldShift = 2; 302 303 const int kFrBits = 5; 304 const int kFrShift = 21; 305 const int kFsShift = 11; 306 const int kFsBits = 5; 307 const int kFtShift = 16; 308 const int kFtBits = 5; 309 const int kFdShift = 6; 310 const int kFdBits = 5; 311 const int kFCccShift = 8; 312 const int kFCccBits = 3; 313 const int kFBccShift = 18; 314 const int kFBccBits = 3; 315 const int kFBtrueShift = 16; 316 const int kFBtrueBits = 1; 317 318 // ----- Miscellaneous useful masks. 319 // Instruction bit masks. 320 const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift; 321 const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; 322 const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift; 323 const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift; 324 const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift; 325 const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift; 326 const int kImm28Mask = ((1 << kImm28Bits) - 1) << kImm28Shift; 327 const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift; 328 const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift; 329 const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; 330 const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift; 331 const int kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift; 332 // Misc masks. 333 const int kHiMask = 0xffff << 16; 334 const int kLoMask = 0xffff; 335 const int kSignMask = 0x80000000; 336 const int kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1; 337 338 // ----- MIPS Opcodes and Function Fields. 339 // We use this presentation to stay close to the table representation in 340 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set. 341 enum Opcode : uint32_t { 342 SPECIAL = 0U << kOpcodeShift, 343 REGIMM = 1U << kOpcodeShift, 344 345 J = ((0U << 3) + 2) << kOpcodeShift, 346 JAL = ((0U << 3) + 3) << kOpcodeShift, 347 BEQ = ((0U << 3) + 4) << kOpcodeShift, 348 BNE = ((0U << 3) + 5) << kOpcodeShift, 349 BLEZ = ((0U << 3) + 6) << kOpcodeShift, 350 BGTZ = ((0U << 3) + 7) << kOpcodeShift, 351 352 ADDI = ((1U << 3) + 0) << kOpcodeShift, 353 ADDIU = ((1U << 3) + 1) << kOpcodeShift, 354 SLTI = ((1U << 3) + 2) << kOpcodeShift, 355 SLTIU = ((1U << 3) + 3) << kOpcodeShift, 356 ANDI = ((1U << 3) + 4) << kOpcodeShift, 357 ORI = ((1U << 3) + 5) << kOpcodeShift, 358 XORI = ((1U << 3) + 6) << kOpcodeShift, 359 LUI = ((1U << 3) + 7) << kOpcodeShift, // LUI/AUI family. 360 361 BEQC = ((2U << 3) + 0) << kOpcodeShift, 362 COP1 = ((2U << 3) + 1) << kOpcodeShift, // Coprocessor 1 class. 363 BEQL = ((2U << 3) + 4) << kOpcodeShift, 364 BNEL = ((2U << 3) + 5) << kOpcodeShift, 365 BLEZL = ((2U << 3) + 6) << kOpcodeShift, 366 BGTZL = ((2U << 3) + 7) << kOpcodeShift, 367 368 DADDI = ((3U << 3) + 0) << kOpcodeShift, // This is also BNEC. 369 SPECIAL2 = ((3U << 3) + 4) << kOpcodeShift, 370 SPECIAL3 = ((3U << 3) + 7) << kOpcodeShift, 371 372 LB = ((4U << 3) + 0) << kOpcodeShift, 373 LH = ((4U << 3) + 1) << kOpcodeShift, 374 LWL = ((4U << 3) + 2) << kOpcodeShift, 375 LW = ((4U << 3) + 3) << kOpcodeShift, 376 LBU = ((4U << 3) + 4) << kOpcodeShift, 377 LHU = ((4U << 3) + 5) << kOpcodeShift, 378 LWR = ((4U << 3) + 6) << kOpcodeShift, 379 SB = ((5U << 3) + 0) << kOpcodeShift, 380 SH = ((5U << 3) + 1) << kOpcodeShift, 381 SWL = ((5U << 3) + 2) << kOpcodeShift, 382 SW = ((5U << 3) + 3) << kOpcodeShift, 383 SWR = ((5U << 3) + 6) << kOpcodeShift, 384 385 LWC1 = ((6U << 3) + 1) << kOpcodeShift, 386 BC = ((6U << 3) + 2) << kOpcodeShift, 387 LDC1 = ((6U << 3) + 5) << kOpcodeShift, 388 POP66 = ((6U << 3) + 6) << kOpcodeShift, // beqzc, jic 389 390 PREF = ((6U << 3) + 3) << kOpcodeShift, 391 392 SWC1 = ((7U << 3) + 1) << kOpcodeShift, 393 BALC = ((7U << 3) + 2) << kOpcodeShift, 394 PCREL = ((7U << 3) + 3) << kOpcodeShift, 395 SDC1 = ((7U << 3) + 5) << kOpcodeShift, 396 POP76 = ((7U << 3) + 6) << kOpcodeShift, // bnezc, jialc 397 398 COP1X = ((1U << 4) + 3) << kOpcodeShift, 399 400 // New r6 instruction. 401 POP06 = BLEZ, // bgeuc/bleuc, blezalc, bgezalc 402 POP07 = BGTZ, // bltuc/bgtuc, bgtzalc, bltzalc 403 POP10 = ADDI, // beqzalc, bovc, beqc 404 POP26 = BLEZL, // bgezc, blezc, bgec/blec 405 POP27 = BGTZL, // bgtzc, bltzc, bltc/bgtc 406 POP30 = DADDI, // bnezalc, bnvc, bnec 407 }; 408 409 enum SecondaryField : uint32_t { 410 // SPECIAL Encoding of Function Field. 411 SLL = ((0U << 3) + 0), 412 MOVCI = ((0U << 3) + 1), 413 SRL = ((0U << 3) + 2), 414 SRA = ((0U << 3) + 3), 415 SLLV = ((0U << 3) + 4), 416 LSA = ((0U << 3) + 5), 417 SRLV = ((0U << 3) + 6), 418 SRAV = ((0U << 3) + 7), 419 420 JR = ((1U << 3) + 0), 421 JALR = ((1U << 3) + 1), 422 MOVZ = ((1U << 3) + 2), 423 MOVN = ((1U << 3) + 3), 424 BREAK = ((1U << 3) + 5), 425 SYNC = ((1U << 3) + 7), 426 427 MFHI = ((2U << 3) + 0), 428 CLZ_R6 = ((2U << 3) + 0), 429 CLO_R6 = ((2U << 3) + 1), 430 MFLO = ((2U << 3) + 2), 431 432 MULT = ((3U << 3) + 0), 433 MULTU = ((3U << 3) + 1), 434 DIV = ((3U << 3) + 2), 435 DIVU = ((3U << 3) + 3), 436 437 ADD = ((4U << 3) + 0), 438 ADDU = ((4U << 3) + 1), 439 SUB = ((4U << 3) + 2), 440 SUBU = ((4U << 3) + 3), 441 AND = ((4U << 3) + 4), 442 OR = ((4U << 3) + 5), 443 XOR = ((4U << 3) + 6), 444 NOR = ((4U << 3) + 7), 445 446 SLT = ((5U << 3) + 2), 447 SLTU = ((5U << 3) + 3), 448 449 TGE = ((6U << 3) + 0), 450 TGEU = ((6U << 3) + 1), 451 TLT = ((6U << 3) + 2), 452 TLTU = ((6U << 3) + 3), 453 TEQ = ((6U << 3) + 4), 454 SELEQZ_S = ((6U << 3) + 5), 455 TNE = ((6U << 3) + 6), 456 SELNEZ_S = ((6U << 3) + 7), 457 458 // Multiply integers in r6. 459 MUL_MUH = ((3U << 3) + 0), // MUL, MUH. 460 MUL_MUH_U = ((3U << 3) + 1), // MUL_U, MUH_U. 461 RINT = ((3U << 3) + 2), 462 463 MUL_OP = ((0U << 3) + 2), 464 MUH_OP = ((0U << 3) + 3), 465 DIV_OP = ((0U << 3) + 2), 466 MOD_OP = ((0U << 3) + 3), 467 468 DIV_MOD = ((3U << 3) + 2), 469 DIV_MOD_U = ((3U << 3) + 3), 470 471 // SPECIAL2 Encoding of Function Field. 472 MUL = ((0U << 3) + 2), 473 CLZ = ((4U << 3) + 0), 474 CLO = ((4U << 3) + 1), 475 476 // SPECIAL3 Encoding of Function Field. 477 EXT = ((0U << 3) + 0), 478 INS = ((0U << 3) + 4), 479 BSHFL = ((4U << 3) + 0), 480 481 // SPECIAL3 Encoding of sa Field. 482 BITSWAP = ((0U << 3) + 0), 483 ALIGN = ((0U << 3) + 2), 484 WSBH = ((0U << 3) + 2), 485 SEB = ((2U << 3) + 0), 486 SEH = ((3U << 3) + 0), 487 488 // REGIMM encoding of rt Field. 489 BLTZ = ((0U << 3) + 0) << 16, 490 BGEZ = ((0U << 3) + 1) << 16, 491 BLTZAL = ((2U << 3) + 0) << 16, 492 BGEZAL = ((2U << 3) + 1) << 16, 493 BGEZALL = ((2U << 3) + 3) << 16, 494 495 // COP1 Encoding of rs Field. 496 MFC1 = ((0U << 3) + 0) << 21, 497 CFC1 = ((0U << 3) + 2) << 21, 498 MFHC1 = ((0U << 3) + 3) << 21, 499 MTC1 = ((0U << 3) + 4) << 21, 500 CTC1 = ((0U << 3) + 6) << 21, 501 MTHC1 = ((0U << 3) + 7) << 21, 502 BC1 = ((1U << 3) + 0) << 21, 503 S = ((2U << 3) + 0) << 21, 504 D = ((2U << 3) + 1) << 21, 505 W = ((2U << 3) + 4) << 21, 506 L = ((2U << 3) + 5) << 21, 507 PS = ((2U << 3) + 6) << 21, 508 // COP1 Encoding of Function Field When rs=S. 509 510 ADD_S = ((0U << 3) + 0), 511 SUB_S = ((0U << 3) + 1), 512 MUL_S = ((0U << 3) + 2), 513 DIV_S = ((0U << 3) + 3), 514 ABS_S = ((0U << 3) + 5), 515 SQRT_S = ((0U << 3) + 4), 516 MOV_S = ((0U << 3) + 6), 517 NEG_S = ((0U << 3) + 7), 518 ROUND_L_S = ((1U << 3) + 0), 519 TRUNC_L_S = ((1U << 3) + 1), 520 CEIL_L_S = ((1U << 3) + 2), 521 FLOOR_L_S = ((1U << 3) + 3), 522 ROUND_W_S = ((1U << 3) + 4), 523 TRUNC_W_S = ((1U << 3) + 5), 524 CEIL_W_S = ((1U << 3) + 6), 525 FLOOR_W_S = ((1U << 3) + 7), 526 RECIP_S = ((2U << 3) + 5), 527 RSQRT_S = ((2U << 3) + 6), 528 CLASS_S = ((3U << 3) + 3), 529 CVT_D_S = ((4U << 3) + 1), 530 CVT_W_S = ((4U << 3) + 4), 531 CVT_L_S = ((4U << 3) + 5), 532 CVT_PS_S = ((4U << 3) + 6), 533 534 // COP1 Encoding of Function Field When rs=D. 535 ADD_D = ((0U << 3) + 0), 536 SUB_D = ((0U << 3) + 1), 537 MUL_D = ((0U << 3) + 2), 538 DIV_D = ((0U << 3) + 3), 539 SQRT_D = ((0U << 3) + 4), 540 ABS_D = ((0U << 3) + 5), 541 MOV_D = ((0U << 3) + 6), 542 NEG_D = ((0U << 3) + 7), 543 ROUND_L_D = ((1U << 3) + 0), 544 TRUNC_L_D = ((1U << 3) + 1), 545 CEIL_L_D = ((1U << 3) + 2), 546 FLOOR_L_D = ((1U << 3) + 3), 547 ROUND_W_D = ((1U << 3) + 4), 548 TRUNC_W_D = ((1U << 3) + 5), 549 CEIL_W_D = ((1U << 3) + 6), 550 FLOOR_W_D = ((1U << 3) + 7), 551 RECIP_D = ((2U << 3) + 5), 552 RSQRT_D = ((2U << 3) + 6), 553 CLASS_D = ((3U << 3) + 3), 554 MIN = ((3U << 3) + 4), 555 MINA = ((3U << 3) + 5), 556 MAX = ((3U << 3) + 6), 557 MAXA = ((3U << 3) + 7), 558 CVT_S_D = ((4U << 3) + 0), 559 CVT_W_D = ((4U << 3) + 4), 560 CVT_L_D = ((4U << 3) + 5), 561 C_F_D = ((6U << 3) + 0), 562 C_UN_D = ((6U << 3) + 1), 563 C_EQ_D = ((6U << 3) + 2), 564 C_UEQ_D = ((6U << 3) + 3), 565 C_OLT_D = ((6U << 3) + 4), 566 C_ULT_D = ((6U << 3) + 5), 567 C_OLE_D = ((6U << 3) + 6), 568 C_ULE_D = ((6U << 3) + 7), 569 570 // COP1 Encoding of Function Field When rs=W or L. 571 CVT_S_W = ((4U << 3) + 0), 572 CVT_D_W = ((4U << 3) + 1), 573 CVT_S_L = ((4U << 3) + 0), 574 CVT_D_L = ((4U << 3) + 1), 575 BC1EQZ = ((2U << 2) + 1) << 21, 576 BC1NEZ = ((3U << 2) + 1) << 21, 577 // COP1 CMP positive predicates Bit 5..4 = 00. 578 CMP_AF = ((0U << 3) + 0), 579 CMP_UN = ((0U << 3) + 1), 580 CMP_EQ = ((0U << 3) + 2), 581 CMP_UEQ = ((0U << 3) + 3), 582 CMP_LT = ((0U << 3) + 4), 583 CMP_ULT = ((0U << 3) + 5), 584 CMP_LE = ((0U << 3) + 6), 585 CMP_ULE = ((0U << 3) + 7), 586 CMP_SAF = ((1U << 3) + 0), 587 CMP_SUN = ((1U << 3) + 1), 588 CMP_SEQ = ((1U << 3) + 2), 589 CMP_SUEQ = ((1U << 3) + 3), 590 CMP_SSLT = ((1U << 3) + 4), 591 CMP_SSULT = ((1U << 3) + 5), 592 CMP_SLE = ((1U << 3) + 6), 593 CMP_SULE = ((1U << 3) + 7), 594 // COP1 CMP negative predicates Bit 5..4 = 01. 595 CMP_AT = ((2U << 3) + 0), // Reserved, not implemented. 596 CMP_OR = ((2U << 3) + 1), 597 CMP_UNE = ((2U << 3) + 2), 598 CMP_NE = ((2U << 3) + 3), 599 CMP_UGE = ((2U << 3) + 4), // Reserved, not implemented. 600 CMP_OGE = ((2U << 3) + 5), // Reserved, not implemented. 601 CMP_UGT = ((2U << 3) + 6), // Reserved, not implemented. 602 CMP_OGT = ((2U << 3) + 7), // Reserved, not implemented. 603 CMP_SAT = ((3U << 3) + 0), // Reserved, not implemented. 604 CMP_SOR = ((3U << 3) + 1), 605 CMP_SUNE = ((3U << 3) + 2), 606 CMP_SNE = ((3U << 3) + 3), 607 CMP_SUGE = ((3U << 3) + 4), // Reserved, not implemented. 608 CMP_SOGE = ((3U << 3) + 5), // Reserved, not implemented. 609 CMP_SUGT = ((3U << 3) + 6), // Reserved, not implemented. 610 CMP_SOGT = ((3U << 3) + 7), // Reserved, not implemented. 611 612 SEL = ((2U << 3) + 0), 613 MOVZ_C = ((2U << 3) + 2), 614 MOVN_C = ((2U << 3) + 3), 615 SELEQZ_C = ((2U << 3) + 4), // COP1 on FPR registers. 616 MOVF = ((2U << 3) + 1), // Function field for MOVT.fmt and MOVF.fmt 617 SELNEZ_C = ((2U << 3) + 7), // COP1 on FPR registers. 618 // COP1 Encoding of Function Field When rs=PS. 619 // COP1X Encoding of Function Field. 620 MADD_D = ((4U << 3) + 1), 621 622 // PCREL Encoding of rt Field. 623 ADDIUPC = ((0U << 2) + 0), 624 LWPC = ((0U << 2) + 1), 625 AUIPC = ((3U << 3) + 6), 626 ALUIPC = ((3U << 3) + 7), 627 628 // POP66 Encoding of rs Field. 629 JIC = ((0U << 5) + 0), 630 631 // POP76 Encoding of rs Field. 632 JIALC = ((0U << 5) + 0), 633 634 NULLSF = 0U 635 }; 636 637 // ----- Emulated conditions. 638 // On MIPS we use this enum to abstract from conditional branch instructions. 639 // The 'U' prefix is used to specify unsigned comparisons. 640 // Opposite conditions must be paired as odd/even numbers 641 // because 'NegateCondition' function flips LSB to negate condition. 642 enum Condition { 643 // Any value < 0 is considered no_condition. 644 kNoCondition = -1, 645 overflow = 0, 646 no_overflow = 1, 647 Uless = 2, 648 Ugreater_equal = 3, 649 Uless_equal = 4, 650 Ugreater = 5, 651 equal = 6, 652 not_equal = 7, // Unordered or Not Equal. 653 negative = 8, 654 positive = 9, 655 parity_even = 10, 656 parity_odd = 11, 657 less = 12, 658 greater_equal = 13, 659 less_equal = 14, 660 greater = 15, 661 ueq = 16, // Unordered or Equal. 662 ogl = 17, // Ordered and Not Equal. 663 cc_always = 18, 664 665 // Aliases. 666 carry = Uless, 667 not_carry = Ugreater_equal, 668 zero = equal, 669 eq = equal, 670 not_zero = not_equal, 671 ne = not_equal, 672 nz = not_equal, 673 sign = negative, 674 not_sign = positive, 675 mi = negative, 676 pl = positive, 677 hi = Ugreater, 678 ls = Uless_equal, 679 ge = greater_equal, 680 lt = less, 681 gt = greater, 682 le = less_equal, 683 hs = Ugreater_equal, 684 lo = Uless, 685 al = cc_always, 686 ult = Uless, 687 uge = Ugreater_equal, 688 ule = Uless_equal, 689 ugt = Ugreater, 690 cc_default = kNoCondition 691 }; 692 693 694 // Returns the equivalent of !cc. 695 // Negation of the default kNoCondition (-1) results in a non-default 696 // no_condition value (-2). As long as tests for no_condition check 697 // for condition < 0, this will work as expected. 698 inline Condition NegateCondition(Condition cc) { 699 DCHECK(cc != cc_always); 700 return static_cast<Condition>(cc ^ 1); 701 } 702 703 704 inline Condition NegateFpuCondition(Condition cc) { 705 DCHECK(cc != cc_always); 706 switch (cc) { 707 case ult: 708 return ge; 709 case ugt: 710 return le; 711 case uge: 712 return lt; 713 case ule: 714 return gt; 715 case lt: 716 return uge; 717 case gt: 718 return ule; 719 case ge: 720 return ult; 721 case le: 722 return ugt; 723 case eq: 724 return ne; 725 case ne: 726 return eq; 727 case ueq: 728 return ogl; 729 case ogl: 730 return ueq; 731 default: 732 return cc; 733 } 734 } 735 736 737 // Commute a condition such that {a cond b == b cond' a}. 738 inline Condition CommuteCondition(Condition cc) { 739 switch (cc) { 740 case Uless: 741 return Ugreater; 742 case Ugreater: 743 return Uless; 744 case Ugreater_equal: 745 return Uless_equal; 746 case Uless_equal: 747 return Ugreater_equal; 748 case less: 749 return greater; 750 case greater: 751 return less; 752 case greater_equal: 753 return less_equal; 754 case less_equal: 755 return greater_equal; 756 default: 757 return cc; 758 } 759 } 760 761 762 // ----- Coprocessor conditions. 763 enum FPUCondition { 764 kNoFPUCondition = -1, 765 766 F = 0x00, // False. 767 UN = 0x01, // Unordered. 768 EQ = 0x02, // Equal. 769 UEQ = 0x03, // Unordered or Equal. 770 OLT = 0x04, // Ordered or Less Than, on Mips release < 6. 771 LT = 0x04, // Ordered or Less Than, on Mips release >= 6. 772 ULT = 0x05, // Unordered or Less Than. 773 OLE = 0x06, // Ordered or Less Than or Equal, on Mips release < 6. 774 LE = 0x06, // Ordered or Less Than or Equal, on Mips release >= 6. 775 ULE = 0x07, // Unordered or Less Than or Equal. 776 777 // Following constants are available on Mips release >= 6 only. 778 ORD = 0x11, // Ordered, on Mips release >= 6. 779 UNE = 0x12, // Not equal, on Mips release >= 6. 780 NE = 0x13, // Ordered Greater Than or Less Than. on Mips >= 6 only. 781 }; 782 783 784 // FPU rounding modes. 785 enum FPURoundingMode { 786 RN = 0 << 0, // Round to Nearest. 787 RZ = 1 << 0, // Round towards zero. 788 RP = 2 << 0, // Round towards Plus Infinity. 789 RM = 3 << 0, // Round towards Minus Infinity. 790 791 // Aliases. 792 kRoundToNearest = RN, 793 kRoundToZero = RZ, 794 kRoundToPlusInf = RP, 795 kRoundToMinusInf = RM, 796 797 mode_round = RN, 798 mode_ceil = RP, 799 mode_floor = RM, 800 mode_trunc = RZ 801 }; 802 803 const uint32_t kFPURoundingModeMask = 3 << 0; 804 805 enum CheckForInexactConversion { 806 kCheckForInexactConversion, 807 kDontCheckForInexactConversion 808 }; 809 810 enum class MaxMinKind : int { kMin = 0, kMax = 1 }; 811 812 // ----------------------------------------------------------------------------- 813 // Hints. 814 815 // Branch hints are not used on the MIPS. They are defined so that they can 816 // appear in shared function signatures, but will be ignored in MIPS 817 // implementations. 818 enum Hint { 819 no_hint = 0 820 }; 821 822 823 inline Hint NegateHint(Hint hint) { 824 return no_hint; 825 } 826 827 828 // ----------------------------------------------------------------------------- 829 // Specific instructions, constants, and masks. 830 // These constants are declared in assembler-mips.cc, as they use named 831 // registers and other constants. 832 833 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) 834 // operations as post-increment of sp. 835 extern const Instr kPopInstruction; 836 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. 837 extern const Instr kPushInstruction; 838 // sw(r, MemOperand(sp, 0)) 839 extern const Instr kPushRegPattern; 840 // lw(r, MemOperand(sp, 0)) 841 extern const Instr kPopRegPattern; 842 extern const Instr kLwRegFpOffsetPattern; 843 extern const Instr kSwRegFpOffsetPattern; 844 extern const Instr kLwRegFpNegOffsetPattern; 845 extern const Instr kSwRegFpNegOffsetPattern; 846 // A mask for the Rt register for push, pop, lw, sw instructions. 847 extern const Instr kRtMask; 848 extern const Instr kLwSwInstrTypeMask; 849 extern const Instr kLwSwInstrArgumentMask; 850 extern const Instr kLwSwOffsetMask; 851 852 // Break 0xfffff, reserved for redirected real time call. 853 const Instr rtCallRedirInstr = SPECIAL | BREAK | call_rt_redirected << 6; 854 // A nop instruction. (Encoding of sll 0 0 0). 855 const Instr nopInstr = 0; 856 857 static constexpr uint64_t OpcodeToBitNumber(Opcode opcode) { 858 return 1ULL << (static_cast<uint32_t>(opcode) >> kOpcodeShift); 859 } 860 861 862 class Instruction { 863 public: 864 enum { 865 kInstrSize = 4, 866 kInstrSizeLog2 = 2, 867 // On MIPS PC cannot actually be directly accessed. We behave as if PC was 868 // always the value of the current instruction being executed. 869 kPCReadOffset = 0 870 }; 871 872 // Get the raw instruction bits. 873 inline Instr InstructionBits() const { 874 return *reinterpret_cast<const Instr*>(this); 875 } 876 877 // Set the raw instruction bits to value. 878 inline void SetInstructionBits(Instr value) { 879 *reinterpret_cast<Instr*>(this) = value; 880 } 881 882 // Read one particular bit out of the instruction bits. 883 inline int Bit(int nr) const { 884 return (InstructionBits() >> nr) & 1; 885 } 886 887 // Read a bit field out of the instruction bits. 888 inline int Bits(int hi, int lo) const { 889 return (InstructionBits() >> lo) & ((2U << (hi - lo)) - 1); 890 } 891 892 // Instruction type. 893 enum Type { 894 kRegisterType, 895 kImmediateType, 896 kJumpType, 897 kUnsupported = -1 898 }; 899 900 enum TypeChecks { NORMAL, EXTRA }; 901 902 903 static constexpr uint64_t kOpcodeImmediateTypeMask = 904 OpcodeToBitNumber(REGIMM) | OpcodeToBitNumber(BEQ) | 905 OpcodeToBitNumber(BNE) | OpcodeToBitNumber(BLEZ) | 906 OpcodeToBitNumber(BGTZ) | OpcodeToBitNumber(ADDI) | 907 OpcodeToBitNumber(DADDI) | OpcodeToBitNumber(ADDIU) | 908 OpcodeToBitNumber(SLTI) | OpcodeToBitNumber(SLTIU) | 909 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) | 910 OpcodeToBitNumber(XORI) | OpcodeToBitNumber(LUI) | 911 OpcodeToBitNumber(BEQL) | OpcodeToBitNumber(BNEL) | 912 OpcodeToBitNumber(BLEZL) | OpcodeToBitNumber(BGTZL) | 913 OpcodeToBitNumber(POP66) | OpcodeToBitNumber(POP76) | 914 OpcodeToBitNumber(LB) | OpcodeToBitNumber(LH) | OpcodeToBitNumber(LWL) | 915 OpcodeToBitNumber(LW) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) | 916 OpcodeToBitNumber(LWR) | OpcodeToBitNumber(SB) | OpcodeToBitNumber(SH) | 917 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SWR) | 918 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) | 919 OpcodeToBitNumber(SWC1) | OpcodeToBitNumber(SDC1) | 920 OpcodeToBitNumber(PCREL) | OpcodeToBitNumber(BC) | 921 OpcodeToBitNumber(BALC); 922 923 #define FunctionFieldToBitNumber(function) (1ULL << function) 924 925 static const uint64_t kFunctionFieldRegisterTypeMask = 926 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) | 927 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) | 928 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(SRA) | 929 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(SRLV) | 930 FunctionFieldToBitNumber(SRAV) | FunctionFieldToBitNumber(LSA) | 931 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) | 932 FunctionFieldToBitNumber(MULT) | FunctionFieldToBitNumber(MULTU) | 933 FunctionFieldToBitNumber(DIV) | FunctionFieldToBitNumber(DIVU) | 934 FunctionFieldToBitNumber(ADD) | FunctionFieldToBitNumber(ADDU) | 935 FunctionFieldToBitNumber(SUB) | FunctionFieldToBitNumber(SUBU) | 936 FunctionFieldToBitNumber(AND) | FunctionFieldToBitNumber(OR) | 937 FunctionFieldToBitNumber(XOR) | FunctionFieldToBitNumber(NOR) | 938 FunctionFieldToBitNumber(SLT) | FunctionFieldToBitNumber(SLTU) | 939 FunctionFieldToBitNumber(TGE) | FunctionFieldToBitNumber(TGEU) | 940 FunctionFieldToBitNumber(TLT) | FunctionFieldToBitNumber(TLTU) | 941 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) | 942 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) | 943 FunctionFieldToBitNumber(MOVCI) | FunctionFieldToBitNumber(SELEQZ_S) | 944 FunctionFieldToBitNumber(SELNEZ_S) | FunctionFieldToBitNumber(SYNC); 945 946 // Get the encoding type of the instruction. 947 inline Type InstructionType(TypeChecks checks = NORMAL) const; 948 949 // Accessors for the different named fields used in the MIPS encoding. 950 inline Opcode OpcodeValue() const { 951 return static_cast<Opcode>( 952 Bits(kOpcodeShift + kOpcodeBits - 1, kOpcodeShift)); 953 } 954 955 inline int RsValue() const { 956 DCHECK(InstructionType() == kRegisterType || 957 InstructionType() == kImmediateType); 958 return Bits(kRsShift + kRsBits - 1, kRsShift); 959 } 960 961 inline int RtValue() const { 962 DCHECK(InstructionType() == kRegisterType || 963 InstructionType() == kImmediateType); 964 return Bits(kRtShift + kRtBits - 1, kRtShift); 965 } 966 967 inline int RdValue() const { 968 DCHECK(InstructionType() == kRegisterType); 969 return Bits(kRdShift + kRdBits - 1, kRdShift); 970 } 971 972 inline int SaValue() const { 973 DCHECK(InstructionType() == kRegisterType); 974 return Bits(kSaShift + kSaBits - 1, kSaShift); 975 } 976 977 inline int LsaSaValue() const { 978 DCHECK(InstructionType() == kRegisterType); 979 return Bits(kSaShift + kLsaSaBits - 1, kSaShift); 980 } 981 982 inline int FunctionValue() const { 983 DCHECK(InstructionType() == kRegisterType || 984 InstructionType() == kImmediateType); 985 return Bits(kFunctionShift + kFunctionBits - 1, kFunctionShift); 986 } 987 988 inline int FdValue() const { 989 return Bits(kFdShift + kFdBits - 1, kFdShift); 990 } 991 992 inline int FsValue() const { 993 return Bits(kFsShift + kFsBits - 1, kFsShift); 994 } 995 996 inline int FtValue() const { 997 return Bits(kFtShift + kFtBits - 1, kFtShift); 998 } 999 1000 inline int FrValue() const { 1001 return Bits(kFrShift + kFrBits -1, kFrShift); 1002 } 1003 1004 inline int Bp2Value() const { 1005 DCHECK(InstructionType() == kRegisterType); 1006 return Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift); 1007 } 1008 1009 // Float Compare condition code instruction bits. 1010 inline int FCccValue() const { 1011 return Bits(kFCccShift + kFCccBits - 1, kFCccShift); 1012 } 1013 1014 // Float Branch condition code instruction bits. 1015 inline int FBccValue() const { 1016 return Bits(kFBccShift + kFBccBits - 1, kFBccShift); 1017 } 1018 1019 // Float Branch true/false instruction bit. 1020 inline int FBtrueValue() const { 1021 return Bits(kFBtrueShift + kFBtrueBits - 1, kFBtrueShift); 1022 } 1023 1024 // Return the fields at their original place in the instruction encoding. 1025 inline Opcode OpcodeFieldRaw() const { 1026 return static_cast<Opcode>(InstructionBits() & kOpcodeMask); 1027 } 1028 1029 inline int RsFieldRaw() const { 1030 DCHECK(InstructionType() == kRegisterType || 1031 InstructionType() == kImmediateType); 1032 return InstructionBits() & kRsFieldMask; 1033 } 1034 1035 // Same as above function, but safe to call within InstructionType(). 1036 inline int RsFieldRawNoAssert() const { 1037 return InstructionBits() & kRsFieldMask; 1038 } 1039 1040 inline int RtFieldRaw() const { 1041 DCHECK(InstructionType() == kRegisterType || 1042 InstructionType() == kImmediateType); 1043 return InstructionBits() & kRtFieldMask; 1044 } 1045 1046 inline int RdFieldRaw() const { 1047 DCHECK(InstructionType() == kRegisterType); 1048 return InstructionBits() & kRdFieldMask; 1049 } 1050 1051 inline int SaFieldRaw() const { 1052 return InstructionBits() & kSaFieldMask; 1053 } 1054 1055 inline int FunctionFieldRaw() const { 1056 return InstructionBits() & kFunctionFieldMask; 1057 } 1058 1059 // Get the secondary field according to the opcode. 1060 inline int SecondaryValue() const { 1061 Opcode op = OpcodeFieldRaw(); 1062 switch (op) { 1063 case SPECIAL: 1064 case SPECIAL2: 1065 return FunctionValue(); 1066 case COP1: 1067 return RsValue(); 1068 case REGIMM: 1069 return RtValue(); 1070 default: 1071 return NULLSF; 1072 } 1073 } 1074 1075 inline int32_t ImmValue(int bits) const { 1076 DCHECK(InstructionType() == kImmediateType); 1077 return Bits(bits - 1, 0); 1078 } 1079 1080 inline int32_t Imm16Value() const { 1081 DCHECK(InstructionType() == kImmediateType); 1082 return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift); 1083 } 1084 1085 inline int32_t Imm18Value() const { 1086 DCHECK(InstructionType() == kImmediateType); 1087 return Bits(kImm18Shift + kImm18Bits - 1, kImm18Shift); 1088 } 1089 1090 inline int32_t Imm19Value() const { 1091 DCHECK(InstructionType() == kImmediateType); 1092 return Bits(kImm19Shift + kImm19Bits - 1, kImm19Shift); 1093 } 1094 1095 inline int32_t Imm21Value() const { 1096 DCHECK(InstructionType() == kImmediateType); 1097 return Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift); 1098 } 1099 1100 inline int32_t Imm26Value() const { 1101 DCHECK((InstructionType() == kJumpType) || 1102 (InstructionType() == kImmediateType)); 1103 return Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift); 1104 } 1105 1106 static bool IsForbiddenAfterBranchInstr(Instr instr); 1107 1108 // Say if the instruction should not be used in a branch delay slot or 1109 // immediately after a compact branch. 1110 inline bool IsForbiddenAfterBranch() const { 1111 return IsForbiddenAfterBranchInstr(InstructionBits()); 1112 } 1113 1114 inline bool IsForbiddenInBranchDelay() const { 1115 return IsForbiddenAfterBranch(); 1116 } 1117 1118 // Say if the instruction 'links'. e.g. jal, bal. 1119 bool IsLinkingInstruction() const; 1120 // Say if the instruction is a break or a trap. 1121 bool IsTrap() const; 1122 1123 // Instructions are read of out a code stream. The only way to get a 1124 // reference to an instruction is to convert a pointer. There is no way 1125 // to allocate or create instances of class Instruction. 1126 // Use the At(pc) function to create references to Instruction. 1127 static Instruction* At(byte* pc) { 1128 return reinterpret_cast<Instruction*>(pc); 1129 } 1130 1131 private: 1132 // We need to prevent the creation of instances of class Instruction. 1133 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 1134 }; 1135 1136 1137 // ----------------------------------------------------------------------------- 1138 // MIPS assembly various constants. 1139 1140 // C/C++ argument slots size. 1141 const int kCArgSlotCount = 4; 1142 const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize; 1143 const int kInvalidStackOffset = -1; 1144 // JS argument slots size. 1145 const int kJSArgsSlotsSize = 0 * Instruction::kInstrSize; 1146 // Assembly builtins argument slots size. 1147 const int kBArgsSlotsSize = 0 * Instruction::kInstrSize; 1148 1149 const int kBranchReturnOffset = 2 * Instruction::kInstrSize; 1150 1151 1152 Instruction::Type Instruction::InstructionType(TypeChecks checks) const { 1153 if (checks == EXTRA) { 1154 if (OpcodeToBitNumber(OpcodeFieldRaw()) & kOpcodeImmediateTypeMask) { 1155 return kImmediateType; 1156 } 1157 } 1158 switch (OpcodeFieldRaw()) { 1159 case SPECIAL: 1160 if (checks == EXTRA) { 1161 if (FunctionFieldToBitNumber(FunctionFieldRaw()) & 1162 kFunctionFieldRegisterTypeMask) { 1163 return kRegisterType; 1164 } else { 1165 return kUnsupported; 1166 } 1167 } else { 1168 return kRegisterType; 1169 } 1170 break; 1171 case SPECIAL2: 1172 switch (FunctionFieldRaw()) { 1173 case MUL: 1174 case CLZ: 1175 return kRegisterType; 1176 default: 1177 return kUnsupported; 1178 } 1179 break; 1180 case SPECIAL3: 1181 switch (FunctionFieldRaw()) { 1182 case INS: 1183 case EXT: 1184 return kRegisterType; 1185 case BSHFL: { 1186 int sa = SaFieldRaw() >> kSaShift; 1187 switch (sa) { 1188 case BITSWAP: 1189 case WSBH: 1190 case SEB: 1191 case SEH: 1192 return kRegisterType; 1193 } 1194 sa >>= kBp2Bits; 1195 switch (sa) { 1196 case ALIGN: 1197 return kRegisterType; 1198 default: 1199 return kUnsupported; 1200 } 1201 } 1202 default: 1203 return kUnsupported; 1204 } 1205 break; 1206 case COP1: // Coprocessor instructions. 1207 switch (RsFieldRawNoAssert()) { 1208 case BC1: // Branch on coprocessor condition. 1209 case BC1EQZ: 1210 case BC1NEZ: 1211 return kImmediateType; 1212 default: 1213 return kRegisterType; 1214 } 1215 break; 1216 case COP1X: 1217 return kRegisterType; 1218 1219 // 26 bits immediate type instructions. e.g.: j imm26. 1220 case J: 1221 case JAL: 1222 return kJumpType; 1223 1224 default: 1225 if (checks == NORMAL) { 1226 return kImmediateType; 1227 } else { 1228 return kUnsupported; 1229 } 1230 } 1231 } 1232 1233 #undef OpcodeToBitNumber 1234 #undef FunctionFieldToBitNumber 1235 } // namespace internal 1236 } // namespace v8 1237 1238 #endif // #ifndef V8_MIPS_CONSTANTS_H_ 1239
