| /external/vixl/src/vixl/a64/ |
| assembler-a64.h | 82 RegList Bit() const {
460 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
601 return (type_ == other.type()) && ((other.Bit() & list_) != 0);
893 // A literal is a 32-bit or 64-bit piece of data stored in the instruction
[all...] |
| instructions-a64.h | 173 int Bit(int pos) const {
441 // Scalar formats. We add the scalar bit to distinguish between scalar and
442 // vector enumerations; the bit is always set in the encoding of scalar ops
492 // The bit positions in the instruction to consider.
566 // Append a "2" to a mnemonic string based of the state of the Q bit.
633 // The logical format map uses one bit (Q) to encode the NEON vector format:
675 // The FP scalar format map assumes one bit (size<0>) is used to encode the
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| /external/llvm/lib/Fuzzer/ |
| FuzzerMutate.cpp | 51 int Bit = Rand(8);
52 char Mask = 1 << Bit;
54 if (X & (1 << Bit))
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| /external/llvm/lib/TableGen/ |
| TGLexer.h | 46 Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List,
|
| Record.cpp | 250 // Can only convert single bit.
289 if (getNumBits() != 1) return nullptr; // Only accept if just one bit!
303 if (auto *Bit = dyn_cast<BitInit>(getBit(i)))
304 Result |= static_cast<int64_t>(Bit->getValue()) << i;
329 if (Init *Bit = getBit(e-i-1))
330 Result += Bit->getAsString();
337 // Fix bit initializer to preserve the behavior that bit reference from a unset
338 // bits initializer will resolve into VarBitInit to keep the field name and bit
365 Init *Bit = CachedInit->getBit(CurBit->getBitNum())
[all...] |
| TGParser.cpp | 110 return Error(Loc, "Initializer is not compatible with bit range");
119 unsigned Bit = BitList[i];
120 if (NewBits[Bit])
121 return Error(Loc, "Cannot set bit #" + Twine(Bit) + " of value '" +
123 NewBits[Bit] = BInit->getBit(i);
136 InitType = (Twine("' of type bit initializer with length ") +
544 /// ParseRangePiece - Parse a bit/value range.
630 /// ParseOptionalBitList - Parse either a bit list in {}'s or nothing.
645 TokError("expected '}' at end of bit list")
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 57 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
177 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
183 /// isCDisp8 - Return true if this signed displacement fits in a 8-bit
187 "Compressed 8-bit displacement is only valid for EVEX inst.");
224 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
238 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
377 assert(is64BitMode(STI) && "Rip-relative addressing requires 64-bit mode");
403 // 16-bit addressing forms of the ModR/M byte have a different encoding for
407 // For 32-bit addressing, the row and column values in Table 2-2 are
410 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 32 // (((X ^ XORValue) + AddValue) >> Bit)
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
39 unsigned Bit;
64 // Classify VT as either 32 or 64 bit.
203 // Type legalization will convert 8- and 16-bit atomic operations into
220 // Handle unsigned 32-bit types as signed 64-bit types.
226 // We have native support for a 64-bit CTLZ, via FLOGR
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| /external/llvm/lib/Transforms/IPO/ |
| LowerBitSets.cpp | 119 // allows us to compress the bitset by only storing one bit per aligned
178 unsigned Bit = 0;
180 if (BitAllocs[I] < BitAllocs[Bit])
181 Bit = I;
183 AllocByteOffset = BitAllocs[Bit];
187 BitAllocs[Bit] = ReqSize;
192 AllocMask = 1 << Bit;
297 /// Build a bit set for BitSet using the object layouts in
329 /// Build a test that bit BitOffset mod sizeof(Bits)*8 is set in
414 /// Build a test that bit BitOffset is set in BSI, wher
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| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 56 inline RegList CPURegister::Bit() const {
365 // Extend modes SXTX and UXTX require a 64-bit register.
482 // SXTX extend mode requires a 64-bit offset register.
1014 // Subtract five from the shift offset, as we need bit 5 from bit_pos.
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| instructions-arm64.h | 21 // The following macros initialize a float/double variable with a bit pattern
23 // symbol is defined as uint32_t/uint64_t initialized with the desired bit
107 int Bit(int pos) const {
328 // The associated immediate is made of the two 16-bit payloads.
457 // - arg_pattern: A set of PrintfArgPattern values, packed into two-bit fields.
471 // The argument pattern is a set of two-bit-fields, each with one of the
|
| /art/compiler/utils/arm/ |
| constants_arm.h | 149 BIC = 14, // Bit Clear
259 // Read one particular bit out of the instruction bits.
260 int Bit(int nr) const {
264 // Read a bit field out of the instruction bits.
294 int RegShiftField() const { return Bit(4); }
306 int BField() const { return Bit(22); }
307 int WField() const { return Bit(21); }
308 int LField() const { return Bit(20); }
316 int SignField() const { return Bit(6); }
317 int HField() const { return Bit(5);
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| /external/llvm/include/llvm/Support/ |
| CommandLine.h | [all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 80 /// BitRecTy - 'bit' - Represent a single bit
93 std::string getAsString() const override { return "bit"; }
232 /// We could pack these a bit tighter by not having the IK_FirstXXXInit
298 /// the bit subscript operator on this initializer, return null.
342 /// bit.
343 virtual Init *getBit(unsigned Bit) const = 0;
345 /// getBitVar - This method is used to retrieve the initializer for bit
349 /// getBitNum - This method is used to retrieve the bit number of a bit
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 541 // We have a 32-bit register
636 // If 64-bit encoding has been forced we can end up with no
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 113 // XformMskToBitPosU5Imm - Returns the bit position which
114 // the single bit 32 bit mask represents.
115 // Used in Clr and Set bit immediate memops.
124 // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
125 // 16 bit mask represents. Used in Clr and Set bit immediate memops.
130 // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 598 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and
661 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | [all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 131 // Instr is merely used by the Assembler to distinguish 32bit integers
132 // representing instructions from usual 32 bit values.
133 // Instruction objects are pointers to 32bit values, and provide methods to
155 BIC = 14 << 21, // Bit Clear.
160 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
208 // Instruction bit masks.
289 // Bit encoding P U W.
301 // Bit encoding P U W .
359 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
360 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature
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| /external/v8/src/ppc/ |
| constants-ppc.h | 90 // Instr is merely used by the Assembler to distinguish 32bit integers
91 // representing instructions from usual 32 bit values.
92 // Instruction objects are pointers to 32bit values, and provide methods to
96 // Opcodes as defined in section 4.2 table 34 (32bit PowerPC)
120 EXT5 = 30 << 26, // Extended code set 5 - 64bit only
282 MTFSB1 = 38 << 1, // Move to FPSCR Bit 1
285 MTFSB0 = 70 << 1, // Move to FPSCR Bit 0
316 // Instruction encoding bit
341 // Instruction bit masks
372 // Record bit
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| /external/clang/lib/CodeGen/ |
| MicrosoftCXXABI.cpp | 189 // The deleting destructors accept an i32 bitfield as a second parameter. Bit
190 // 1 indicates if the memory should be deleted. Bit 2 indicates if the this
192 // bit 2 is zero, and therefore does not contain a loop.
729 // _CxxThrowException is stdcall on 32-bit x86 platforms.
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 499 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
[all...] |
| /external/v8/src/s390/ |
| constants-s390.h | 151 // Instr is merely used by the Assembler to distinguish 32bit integers
152 // representing instructions from usual 32 bit values.
153 // Instruction objects are pointers to 32bit values, and provide methods to
[all...] |
