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      1 /* libs/pixelflinger/codeflinger/MIPSAssembler.h
      2 **
      3 ** Copyright 2012, The Android Open Source Project
      4 **
      5 ** Licensed under the Apache License, Version 2.0 (the "License");
      6 ** you may not use this file except in compliance with the License.
      7 ** You may obtain a copy of the License at
      8 **
      9 **     http://www.apache.org/licenses/LICENSE-2.0
     10 **
     11 ** Unless required by applicable law or agreed to in writing, software
     12 ** distributed under the License is distributed on an "AS IS" BASIS,
     13 ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     14 ** See the License for the specific language governing permissions and
     15 ** limitations under the License.
     16 */
     17 
     18 #ifndef ANDROID_MIPSASSEMBLER_H
     19 #define ANDROID_MIPSASSEMBLER_H
     20 
     21 #include <stdint.h>
     22 #include <sys/types.h>
     23 
     24 #include "tinyutils/smartpointer.h"
     25 #include "utils/KeyedVector.h"
     26 #include "utils/Vector.h"
     27 
     28 #include "ARMAssemblerInterface.h"
     29 #include "CodeCache.h"
     30 
     31 namespace android {
     32 
     33 class MIPSAssembler;    // forward reference
     34 
     35 // this class mimics ARMAssembler interface
     36 //  intent is to translate each ARM instruction to 1 or more MIPS instr
     37 //  implementation calls MIPSAssembler class to generate mips code
     38 class ArmToMipsAssembler : public ARMAssemblerInterface
     39 {
     40 public:
     41                 ArmToMipsAssembler(const sp<Assembly>& assembly,
     42                         char *abuf = 0, int linesz = 0, int instr_count = 0);
     43     virtual     ~ArmToMipsAssembler();
     44 
     45     uint32_t*   base() const;
     46     uint32_t*   pc() const;
     47     void        disassemble(const char* name);
     48 
     49     virtual void    reset();
     50 
     51     virtual int     generate(const char* name);
     52     virtual int     getCodegenArch();
     53 
     54     virtual void    prolog();
     55     virtual void    epilog(uint32_t touched);
     56     virtual void    comment(const char* string);
     57 
     58 
     59     // -----------------------------------------------------------------------
     60     // shifters and addressing modes
     61     // -----------------------------------------------------------------------
     62 
     63     // shifters...
     64     virtual bool        isValidImmediate(uint32_t immed);
     65     virtual int         buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm);
     66 
     67     virtual uint32_t    imm(uint32_t immediate);
     68     virtual uint32_t    reg_imm(int Rm, int type, uint32_t shift);
     69     virtual uint32_t    reg_rrx(int Rm);
     70     virtual uint32_t    reg_reg(int Rm, int type, int Rs);
     71 
     72     // addressing modes...
     73     // LDR(B)/STR(B)/PLD
     74     // (immediate and Rm can be negative, which indicates U=0)
     75     virtual uint32_t    immed12_pre(int32_t immed12, int W=0);
     76     virtual uint32_t    immed12_post(int32_t immed12);
     77     virtual uint32_t    reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
     78     virtual uint32_t    reg_scale_post(int Rm, int type=0, uint32_t shift=0);
     79 
     80     // LDRH/LDRSB/LDRSH/STRH
     81     // (immediate and Rm can be negative, which indicates U=0)
     82     virtual uint32_t    immed8_pre(int32_t immed8, int W=0);
     83     virtual uint32_t    immed8_post(int32_t immed8);
     84     virtual uint32_t    reg_pre(int Rm, int W=0);
     85     virtual uint32_t    reg_post(int Rm);
     86 
     87 
     88 
     89 
     90     virtual void    dataProcessing(int opcode, int cc, int s,
     91                                 int Rd, int Rn,
     92                                 uint32_t Op2);
     93     virtual void MLA(int cc, int s,
     94                 int Rd, int Rm, int Rs, int Rn);
     95     virtual void MUL(int cc, int s,
     96                 int Rd, int Rm, int Rs);
     97     virtual void UMULL(int cc, int s,
     98                 int RdLo, int RdHi, int Rm, int Rs);
     99     virtual void UMUAL(int cc, int s,
    100                 int RdLo, int RdHi, int Rm, int Rs);
    101     virtual void SMULL(int cc, int s,
    102                 int RdLo, int RdHi, int Rm, int Rs);
    103     virtual void SMUAL(int cc, int s,
    104                 int RdLo, int RdHi, int Rm, int Rs);
    105 
    106     virtual void B(int cc, uint32_t* pc);
    107     virtual void BL(int cc, uint32_t* pc);
    108     virtual void BX(int cc, int Rn);
    109     virtual void label(const char* theLabel);
    110     virtual void B(int cc, const char* label);
    111     virtual void BL(int cc, const char* label);
    112 
    113     virtual uint32_t* pcForLabel(const char* label);
    114 
    115     virtual void LDR (int cc, int Rd,
    116                 int Rn, uint32_t offset = 0);
    117     virtual void LDRB(int cc, int Rd,
    118                 int Rn, uint32_t offset = 0);
    119     virtual void STR (int cc, int Rd,
    120                 int Rn, uint32_t offset = 0);
    121     virtual void STRB(int cc, int Rd,
    122                 int Rn, uint32_t offset = 0);
    123     virtual void LDRH (int cc, int Rd,
    124                 int Rn, uint32_t offset = 0);
    125     virtual void LDRSB(int cc, int Rd,
    126                 int Rn, uint32_t offset = 0);
    127     virtual void LDRSH(int cc, int Rd,
    128                 int Rn, uint32_t offset = 0);
    129     virtual void STRH (int cc, int Rd,
    130                 int Rn, uint32_t offset = 0);
    131 
    132     virtual void LDM(int cc, int dir,
    133                 int Rn, int W, uint32_t reg_list);
    134     virtual void STM(int cc, int dir,
    135                 int Rn, int W, uint32_t reg_list);
    136 
    137     virtual void SWP(int cc, int Rn, int Rd, int Rm);
    138     virtual void SWPB(int cc, int Rn, int Rd, int Rm);
    139     virtual void SWI(int cc, uint32_t comment);
    140 
    141     virtual void PLD(int Rn, uint32_t offset);
    142     virtual void CLZ(int cc, int Rd, int Rm);
    143     virtual void QADD(int cc, int Rd, int Rm, int Rn);
    144     virtual void QDADD(int cc, int Rd, int Rm, int Rn);
    145     virtual void QSUB(int cc, int Rd, int Rm, int Rn);
    146     virtual void QDSUB(int cc, int Rd, int Rm, int Rn);
    147     virtual void SMUL(int cc, int xy,
    148                 int Rd, int Rm, int Rs);
    149     virtual void SMULW(int cc, int y,
    150                 int Rd, int Rm, int Rs);
    151     virtual void SMLA(int cc, int xy,
    152                 int Rd, int Rm, int Rs, int Rn);
    153     virtual void SMLAL(int cc, int xy,
    154                 int RdHi, int RdLo, int Rs, int Rm);
    155     virtual void SMLAW(int cc, int y,
    156                 int Rd, int Rm, int Rs, int Rn);
    157 
    158     // byte/half word extract...
    159     virtual void UXTB16(int cc, int Rd, int Rm, int rotate);
    160 
    161     // bit manipulation...
    162     virtual void UBFX(int cc, int Rd, int Rn, int lsb, int width);
    163 
    164     // this is some crap to share is MIPSAssembler class for debug
    165     char *      mArmDisassemblyBuffer;
    166     int         mArmLineLength;
    167     int         mArmInstrCount;
    168 
    169     int         mInum;      // current arm instuction number (0..n)
    170     uint32_t**  mArmPC;     // array: PC for 1st mips instr of
    171                             //      each translated ARM instr
    172 
    173 
    174 private:
    175     ArmToMipsAssembler(const ArmToMipsAssembler& rhs);
    176     ArmToMipsAssembler& operator = (const ArmToMipsAssembler& rhs);
    177 
    178     void init_conditional_labels(void);
    179 
    180     void protectConditionalOperands(int Rd);
    181 
    182     // reg__tmp set to MIPS AT, reg 1
    183     int dataProcAdrModes(int op, int& source, bool sign = false, int reg_tmp = 1);
    184 
    185     sp<Assembly>        mAssembly;
    186     MIPSAssembler*      mMips;
    187 
    188 
    189     enum misc_constants_t {
    190         ARM_MAX_INSTUCTIONS = 512  // based on ASSEMBLY_SCRATCH_SIZE
    191     };
    192 
    193     enum {
    194         SRC_REG = 0,
    195         SRC_IMM,
    196         SRC_ERROR = -1
    197     };
    198 
    199     enum addr_modes {
    200         // start above the range of legal mips reg #'s (0-31)
    201         AMODE_REG = 0x20,
    202         AMODE_IMM, AMODE_REG_IMM,               // for data processing
    203         AMODE_IMM_12_PRE, AMODE_IMM_12_POST,    // for load/store
    204         AMODE_REG_SCALE_PRE, AMODE_IMM_8_PRE,
    205         AMODE_IMM_8_POST, AMODE_REG_PRE,
    206         AMODE_UNSUPPORTED
    207     };
    208 
    209     struct addr_mode_t {    // address modes for current ARM instruction
    210         int         reg;
    211         int         stype;
    212         uint32_t    value;
    213         bool        writeback;  // writeback the adr reg after modification
    214     } amode;
    215 
    216     enum cond_types {
    217         CMP_COND = 1,
    218         SBIT_COND
    219     };
    220 
    221     struct cond_mode_t {    // conditional-execution info for current ARM instruction
    222         cond_types  type;
    223         int         r1;
    224         int         r2;
    225         int         labelnum;
    226         char        label[100][10];
    227     } cond;
    228 
    229 };
    230 
    231 
    232 
    233 
    234 // ----------------------------------------------------------------------------
    235 // ----------------------------------------------------------------------------
    236 // ----------------------------------------------------------------------------
    237 
    238 // This is the basic MIPS assembler, which just creates the opcodes in memory.
    239 // All the more complicated work is done in ArmToMipsAssember above.
    240 
    241 class MIPSAssembler
    242 {
    243 public:
    244                 MIPSAssembler(const sp<Assembly>& assembly, ArmToMipsAssembler *parent);
    245                 MIPSAssembler(void* assembly);
    246     virtual     ~MIPSAssembler();
    247 
    248     virtual uint32_t*   base() const;
    249     virtual uint32_t*   pc() const;
    250     virtual void        reset();
    251 
    252     virtual void        disassemble(const char* name);
    253 
    254     virtual void        prolog();
    255     virtual void        epilog(uint32_t touched);
    256     virtual int         generate(const char* name);
    257     virtual void        comment(const char* string);
    258     virtual void        label(const char* string);
    259 
    260     // valid only after generate() has been called
    261     virtual uint32_t*   pcForLabel(const char* label);
    262 
    263 
    264     // ------------------------------------------------------------------------
    265     // MIPSAssemblerInterface...
    266     // ------------------------------------------------------------------------
    267 
    268 #if 0
    269 #pragma mark -
    270 #pragma mark Arithmetic...
    271 #endif
    272 
    273     void ADDU(int Rd, int Rs, int Rt);
    274     void ADDIU(int Rt, int Rs, int16_t imm);
    275     void SUBU(int Rd, int Rs, int Rt);
    276     void SUBIU(int Rt, int Rs, int16_t imm);
    277     void NEGU(int Rd, int Rs);
    278     void MUL(int Rd, int Rs, int Rt);
    279     void MULT(int Rs, int Rt);      // dest is hi,lo
    280     void MULTU(int Rs, int Rt);     // dest is hi,lo
    281     void MADD(int Rs, int Rt);      // hi,lo = hi,lo + Rs * Rt
    282     void MADDU(int Rs, int Rt);     // hi,lo = hi,lo + Rs * Rt
    283     void MSUB(int Rs, int Rt);      // hi,lo = hi,lo - Rs * Rt
    284     void MSUBU(int Rs, int Rt);     // hi,lo = hi,lo - Rs * Rt
    285     void SEB(int Rd, int Rt);       // sign-extend byte (mips32r2)
    286     void SEH(int Rd, int Rt);       // sign-extend half-word (mips32r2)
    287 
    288 
    289 #if 0
    290 #pragma mark -
    291 #pragma mark Comparisons...
    292 #endif
    293 
    294     void SLT(int Rd, int Rs, int Rt);
    295     void SLTI(int Rt, int Rs, int16_t imm);
    296     void SLTU(int Rd, int Rs, int Rt);
    297     void SLTIU(int Rt, int Rs, int16_t imm);
    298 
    299 
    300 #if 0
    301 #pragma mark -
    302 #pragma mark Logical...
    303 #endif
    304 
    305     void AND(int Rd, int Rs, int Rt);
    306     void ANDI(int Rd, int Rs, uint16_t imm);
    307     void OR(int Rd, int Rs, int Rt);
    308     void ORI(int Rt, int Rs, uint16_t imm);
    309     void NOR(int Rd, int Rs, int Rt);
    310     void NOT(int Rd, int Rs);
    311     void XOR(int Rd, int Rs, int Rt);
    312     void XORI(int Rt, int Rs, uint16_t imm);
    313 
    314     void SLL(int Rd, int Rt, int shft);
    315     void SLLV(int Rd, int Rt, int Rs);
    316     void SRL(int Rd, int Rt, int shft);
    317     void SRLV(int Rd, int Rt, int Rs);
    318     void SRA(int Rd, int Rt, int shft);
    319     void SRAV(int Rd, int Rt, int Rs);
    320     void ROTR(int Rd, int Rt, int shft);    // mips32r2
    321     void ROTRV(int Rd, int Rt, int Rs);     // mips32r2
    322     void RORsyn(int Rd, int Rs, int Rt);    // synthetic: d = s rotated by t
    323     void RORIsyn(int Rd, int Rt, int rot);  // synthetic: d = s rotated by immed
    324 
    325     void CLO(int Rd, int Rs);
    326     void CLZ(int Rd, int Rs);
    327     void WSBH(int Rd, int Rt);
    328 
    329 
    330 #if 0
    331 #pragma mark -
    332 #pragma mark Load/store...
    333 #endif
    334 
    335     void LW(int Rt, int Rbase, int16_t offset);
    336     void SW(int Rt, int Rbase, int16_t offset);
    337     void LB(int Rt, int Rbase, int16_t offset);
    338     void LBU(int Rt, int Rbase, int16_t offset);
    339     void SB(int Rt, int Rbase, int16_t offset);
    340     void LH(int Rt, int Rbase, int16_t offset);
    341     void LHU(int Rt, int Rbase, int16_t offset);
    342     void SH(int Rt, int Rbase, int16_t offset);
    343     void LUI(int Rt, int16_t offset);
    344 
    345 #if 0
    346 #pragma mark -
    347 #pragma mark Register moves...
    348 #endif
    349 
    350     void MOVE(int Rd, int Rs);
    351     void MOVN(int Rd, int Rs, int Rt);
    352     void MOVZ(int Rd, int Rs, int Rt);
    353     void MFHI(int Rd);
    354     void MFLO(int Rd);
    355     void MTHI(int Rs);
    356     void MTLO(int Rs);
    357 
    358 #if 0
    359 #pragma mark -
    360 #pragma mark Branch...
    361 #endif
    362 
    363     void B(const char* label);
    364     void BEQ(int Rs, int Rt, const char* label);
    365     void BNE(int Rs, int Rt, const char* label);
    366     void BGEZ(int Rs, const char* label);
    367     void BGTZ(int Rs, const char* label);
    368     void BLEZ(int Rs, const char* label);
    369     void BLTZ(int Rs, const char* label);
    370     void JR(int Rs);
    371 
    372 
    373 #if 0
    374 #pragma mark -
    375 #pragma mark Synthesized Branch...
    376 #endif
    377 
    378     // synthetic variants of above (using slt & friends)
    379     void BEQZ(int Rs, const char* label);
    380     void BNEZ(int Rs, const char* label);
    381     void BGE(int Rs, int Rt, const char* label);
    382     void BGEU(int Rs, int Rt, const char* label);
    383     void BGT(int Rs, int Rt, const char* label);
    384     void BGTU(int Rs, int Rt, const char* label);
    385     void BLE(int Rs, int Rt, const char* label);
    386     void BLEU(int Rs, int Rt, const char* label);
    387     void BLT(int Rs, int Rt, const char* label);
    388     void BLTU(int Rs, int Rt, const char* label);
    389 
    390 #if 0
    391 #pragma mark -
    392 #pragma mark Misc...
    393 #endif
    394 
    395     void NOP(void);
    396     void NOP2(void);
    397     void UNIMPL(void);
    398 
    399 
    400 
    401 
    402 
    403 protected:
    404     virtual void string_detab(char *s);
    405     virtual void string_pad(char *s, int padded_len);
    406 
    407     ArmToMipsAssembler *mParent;
    408     sp<Assembly>    mAssembly;
    409     uint32_t*       mBase;
    410     uint32_t*       mPC;
    411     uint32_t*       mPrologPC;
    412     int64_t         mDuration;
    413 #if defined(WITH_LIB_HARDWARE)
    414     bool            mQemuTracing;
    415 #endif
    416 
    417     struct branch_target_t {
    418         inline branch_target_t() : label(0), pc(0) { }
    419         inline branch_target_t(const char* l, uint32_t* p)
    420             : label(l), pc(p) { }
    421         const char* label;
    422         uint32_t*   pc;
    423     };
    424 
    425     Vector<branch_target_t>                 mBranchTargets;
    426     KeyedVector< const char*, uint32_t* >   mLabels;
    427     KeyedVector< uint32_t*, const char* >   mLabelsInverseMapping;
    428     KeyedVector< uint32_t*, const char* >   mComments;
    429 
    430 
    431 
    432 
    433     // opcode field of all instructions
    434     enum opcode_field {
    435         spec_op, regimm_op, j_op, jal_op,           // 00
    436         beq_op, bne_op, blez_op, bgtz_op,
    437         addi_op, addiu_op, slti_op, sltiu_op,       // 08
    438         andi_op, ori_op, xori_op, lui_op,
    439         cop0_op, cop1_op, cop2_op, cop1x_op,        // 10
    440         beql_op, bnel_op, blezl_op, bgtzl_op,
    441         daddi_op, daddiu_op, ldl_op, ldr_op,        // 18
    442         spec2_op, jalx_op, mdmx_op, spec3_op,
    443         lb_op, lh_op, lwl_op, lw_op,                // 20
    444         lbu_op, lhu_op, lwr_op, lwu_op,
    445         sb_op, sh_op, swl_op, sw_op,                // 28
    446         sdl_op, sdr_op, swr_op, cache_op,
    447         ll_op, lwc1_op, lwc2_op, pref_op,           // 30
    448         lld_op, ldc1_op, ldc2_op, ld_op,
    449         sc_op, swc1_op, swc2_op, rsrv_3b_op,        // 38
    450         scd_op, sdc1_op, sdc2_op, sd_op
    451     };
    452 
    453 
    454     // func field for special opcode
    455     enum func_spec_op {
    456         sll_fn, movc_fn, srl_fn, sra_fn,            // 00
    457         sllv_fn, pmon_fn, srlv_fn, srav_fn,
    458         jr_fn, jalr_fn, movz_fn, movn_fn,           // 08
    459         syscall_fn, break_fn, spim_fn, sync_fn,
    460         mfhi_fn, mthi_fn, mflo_fn, mtlo_fn,         // 10
    461         dsllv_fn, rsrv_spec_2, dsrlv_fn, dsrav_fn,
    462         mult_fn, multu_fn, div_fn, divu_fn,         // 18
    463         dmult_fn, dmultu_fn, ddiv_fn, ddivu_fn,
    464         add_fn, addu_fn, sub_fn, subu_fn,           // 20
    465         and_fn, or_fn, xor_fn, nor_fn,
    466         rsrv_spec_3, rsrv_spec_4, slt_fn, sltu_fn,  // 28
    467         dadd_fn, daddu_fn, dsub_fn, dsubu_fn,
    468         tge_fn, tgeu_fn, tlt_fn, tltu_fn,           // 30
    469         teq_fn, rsrv_spec_5, tne_fn, rsrv_spec_6,
    470         dsll_fn, rsrv_spec_7, dsrl_fn, dsra_fn,     // 38
    471         dsll32_fn, rsrv_spec_8, dsrl32_fn, dsra32_fn
    472     };
    473 
    474     // func field for spec2 opcode
    475     enum func_spec2_op {
    476         madd_fn, maddu_fn, mul_fn, rsrv_spec2_3,
    477         msub_fn, msubu_fn,
    478         clz_fn = 0x20, clo_fn,
    479         dclz_fn = 0x24, dclo_fn,
    480         sdbbp_fn = 0x3f
    481     };
    482 
    483     // func field for spec3 opcode
    484     enum func_spec3_op {
    485         ext_fn, dextm_fn, dextu_fn, dext_fn,
    486         ins_fn, dinsm_fn, dinsu_fn, dins_fn,
    487         bshfl_fn = 0x20,
    488         dbshfl_fn = 0x24,
    489         rdhwr_fn = 0x3b
    490     };
    491 
    492     // sa field for spec3 opcodes, with BSHFL function
    493     enum func_spec3_bshfl {
    494         wsbh_fn = 0x02,
    495         seb_fn = 0x10,
    496         seh_fn = 0x18
    497     };
    498 
    499     // rt field of regimm opcodes.
    500     enum regimm_fn {
    501         bltz_fn, bgez_fn, bltzl_fn, bgezl_fn,
    502         rsrv_ri_fn4, rsrv_ri_fn5, rsrv_ri_fn6, rsrv_ri_fn7,
    503         tgei_fn, tgeiu_fn, tlti_fn, tltiu_fn,
    504         teqi_fn, rsrv_ri_fn_0d, tnei_fn, rsrv_ri_fn0f,
    505         bltzal_fn, bgezal_fn, bltzall_fn, bgezall_fn,
    506         bposge32_fn= 0x1c,
    507         synci_fn = 0x1f
    508     };
    509 
    510 
    511     // func field for mad opcodes (MIPS IV).
    512     enum mad_func {
    513         madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
    514         nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
    515     };
    516 
    517 
    518     enum mips_inst_shifts {
    519         OP_SHF       = 26,
    520         JTARGET_SHF  = 0,
    521         RS_SHF       = 21,
    522         RT_SHF       = 16,
    523         RD_SHF       = 11,
    524         RE_SHF       = 6,
    525         SA_SHF       = RE_SHF,  // synonym
    526         IMM_SHF      = 0,
    527         FUNC_SHF     = 0,
    528 
    529         // mask values
    530         MSK_16       = 0xffff,
    531 
    532 
    533         CACHEOP_SHF  = 18,
    534         CACHESEL_SHF = 16,
    535     };
    536 };
    537 
    538 enum mips_regnames {
    539     R_zero = 0,
    540             R_at,   R_v0,   R_v1,   R_a0,   R_a1,   R_a2,   R_a3,
    541 #if __mips_isa_rev < 6
    542     R_t0,   R_t1,   R_t2,   R_t3,   R_t4,   R_t5,   R_t6,   R_t7,
    543 #else
    544     R_a4,   R_a5,   R_a6,   R_a7,   R_t0,   R_t1,   R_t2,   R_t3,
    545 #endif
    546     R_s0,   R_s1,   R_s2,   R_s3,   R_s4,   R_s5,   R_s6,   R_s7,
    547     R_t8,   R_t9,   R_k0,   R_k1,   R_gp,   R_sp,   R_s8,   R_ra,
    548     R_lr = R_s8,
    549 
    550     // arm regs 0-15 are mips regs 2-17 (meaning s0 & s1 are used)
    551     R_at2  = R_s2,    // R_at2 = 18 = s2
    552     R_cmp  = R_s3,    // R_cmp = 19 = s3
    553     R_cmp2 = R_s4     // R_cmp2 = 20 = s4
    554 };
    555 
    556 
    557 
    558 }; // namespace android
    559 
    560 #endif //ANDROID_MIPSASSEMBLER_H
    561