/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64AsmBackend.cpp | 371 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); 388 Reg1 = getXRegFromWReg(Reg1); 391 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && 394 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && 397 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && 400 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && 403 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && 407 Reg1 = getDRegFromBReg(Reg1); [all...] |
/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2); 600 uint16_t Reg1; 602 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} 606 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 622 Reg0 = Reg1; 623 Reg1 = 0;
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/art/compiler/utils/arm/ |
assembler_arm_test.h | 77 template <typename Reg1, typename Reg2> 78 std::string RepeatTemplatedRRIIC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond), 79 const std::vector<Reg1*> reg1_registers, 81 std::string (AssemblerArmTest::*GetName1)(const Reg1&), 128 for (auto reg1 : reg1_registers) { 131 std::string reg1_string = (this->*GetName1)(*reg1); 153 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c); 174 template <typename Reg1, typename Reg2> 175 std::string RepeatTemplatedRRiiC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond), 176 const std::vector<Reg1*> reg1_registers [all...] |
/external/llvm/lib/Target/Mips/ |
MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2); 76 unsigned Reg1, unsigned Reg2, unsigned Reg3); 79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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MipsAsmPrinter.cpp | 791 unsigned Opcode, unsigned Reg1, 800 unsigned Temp = Reg1; 801 Reg1 = Reg2; 805 I.addOperand(MCOperand::createReg(Reg1)); 811 unsigned Opcode, unsigned Reg1, 815 I.addOperand(MCOperand::createReg(Reg1)); 822 unsigned MovOpc, unsigned Reg1, 826 unsigned temp = Reg1; 827 Reg1 = Reg2; 830 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1) [all...] |
Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
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Mips16InstrInfo.cpp | 265 unsigned Reg1, unsigned Reg2) const { 268 // li reg1, constant 270 // add reg1, reg1, reg2 271 // move sp, reg1 274 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); 278 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); 279 MIB3.addReg(Reg1); 283 MIB4.addReg(Reg1, RegState::Kill);
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MipsSEFrameLowering.cpp | 442 unsigned Reg1 = 446 std::swap(Reg0, Reg1); 454 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); 459 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; 462 std::swap(Reg0, Reg1); 470 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); [all...] |
/art/compiler/utils/ |
assembler_test.h | 141 template <typename Reg1, typename Reg2, typename ImmType> 142 std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, ImmType), 144 const std::vector<Reg1*> reg1_registers, 146 std::string (AssemblerTest::*GetName1)(const Reg1&), 152 for (auto reg1 : reg1_registers) { 156 (assembler_.get()->*f)(*reg1, *reg2, new_imm); 159 std::string reg1_string = (this->*GetName1)(*reg1); 191 template <typename ImmType, typename Reg1, typename Reg2> 192 std::string RepeatTemplatedImmBitsRegisters(void (Ass::*f)(ImmType, Reg1, Reg2), 193 const std::vector<Reg1*> reg1_registers [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 116 unsigned Reg1, bool isKill1, 118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
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/external/llvm/lib/CodeGen/ |
AggressiveAntiDepBreaker.h | 98 // Union Reg1's and Reg2's groups to form a new group. 100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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TargetInstrInfo.cpp | 140 unsigned Reg1 = MI->getOperand(Idx1).getReg(); 153 if (HasDef && Reg0 == Reg1 && 161 Reg0 = Reg1; 175 MI->getOperand(Idx2).setReg(Reg1); [all...] |
AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) 85 unsigned Group1 = GetGroup(Reg1); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FrameLowering.cpp | 738 unsigned Reg1 = CSI[idx].getReg(); 760 if (AArch64::GPR64RegClass.contains(Reg1)) { 768 } else if (AArch64::FPR64RegClass.contains(Reg1)) { [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelDAGToDAG.cpp | 227 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); 251 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); 266 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
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/external/llvm/lib/Target/ARM/ |
A15SDOptimizer.cpp | 89 unsigned Reg1, unsigned Reg2); 469 unsigned Reg1, unsigned Reg2) { 475 .addReg(Reg1)
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Thumb2SizeReduction.cpp | 659 unsigned Reg1 = MI->getOperand(1).getReg(); 664 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) 670 if (Reg1 != Reg0) 677 } else if (Reg0 != Reg1) { [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 488 unsigned Reg1 = Reg; 493 .addReg(Reg1, RegState::Kill) 533 unsigned Reg1 = Reg; 539 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 577 unsigned Reg1 = Reg; 582 .addReg(Reg1, RegState::Kill) [all...] |
PPCVSXSwapRemoval.cpp | 837 unsigned Reg1 = MI->getOperand(1).getReg(); 840 MI->getOperand(2).setReg(Reg1); [all...] |
PPCInstrInfo.cpp | 349 unsigned Reg1 = MI->getOperand(1).getReg(); 358 if (Reg0 == Reg1) { 383 .addReg(Reg1, getKillRegState(Reg1IsKill)) 392 MI->getOperand(2).setReg(Reg1); [all...] |
/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | 100 bool contains(unsigned Reg1, unsigned Reg2) const { 101 return MC->contains(Reg1, Reg2); [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/AsmParser/ |
HexagonAsmParser.cpp | [all...] |
/external/llvm/utils/TableGen/ |
CodeGenRegisters.cpp | [all...] |
/external/llvm/lib/MC/ |
MCDwarf.cpp | [all...] |