| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 378 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
389 Reg2 = getXRegFromWReg(Reg2);
391 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
394 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
397 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
400 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
403 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
408 Reg2 = getDRegFromBReg(Reg2);
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm_test.h | 77 template <typename Reg1, typename Reg2>
78 std::string RepeatTemplatedRRIIC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
80 const std::vector<Reg2*> reg2_registers,
82 std::string (AssemblerArmTest::*GetName2)(const Reg2&),
137 for (auto reg2 : reg2_registers) {
140 std::string reg2_string = (this->*GetName2)(*reg2);
153 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c);
174 template <typename Reg1, typename Reg2>
175 std::string RepeatTemplatedRRiiC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
177 const std::vector<Reg2*> reg2_registers
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.h | 73 unsigned Reg1, unsigned Reg2);
76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
79 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
|
| MipsAsmPrinter.cpp | 792 unsigned Reg2) {
801 Reg1 = Reg2;
802 Reg2 = Temp;
806 I.addOperand(MCOperand::createReg(Reg2));
812 unsigned Reg2, unsigned Reg3) {
816 I.addOperand(MCOperand::createReg(Reg2));
823 unsigned Reg2, unsigned FPReg1,
827 Reg1 = Reg2;
828 Reg2 = temp;
831 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2)
[all...] |
| Mips16InstrInfo.h | 117 unsigned Reg1, unsigned Reg2) const;
|
| Mips16InstrInfo.cpp | 265 unsigned Reg1, unsigned Reg2) const {
269 // move reg2, sp
270 // add reg1, reg1, reg2
276 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
280 MIB3.addReg(Reg2, RegState::Kill);
|
| MipsISelLowering.cpp | 640 // addiu $reg2, $reg1, y-1
647 // addiu $reg2, $reg1, y-1
[all...] |
| /art/compiler/utils/ |
| assembler_test.h | 141 template <typename Reg1, typename Reg2, typename ImmType>
142 std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, ImmType),
145 const std::vector<Reg2*> reg2_registers,
147 std::string (AssemblerTest::*GetName2)(const Reg2&),
153 for (auto reg2 : reg2_registers) {
156 (assembler_.get()->*f)(*reg1, *reg2, new_imm);
165 std::string reg2_string = (this->*GetName2)(*reg2);
191 template <typename ImmType, typename Reg1, typename Reg2>
192 std::string RepeatTemplatedImmBitsRegisters(void (Ass::*f)(ImmType, Reg1, Reg2),
194 const std::vector<Reg2*> reg2_registers
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) {
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 98 // Union Reg1's and Reg2's groups to form a new group.
100 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
| TargetInstrInfo.cpp | 141 unsigned Reg2 = MI->getOperand(Idx2).getReg();
156 Reg0 = Reg2;
158 } else if (HasDef && Reg0 == Reg2 &&
176 MI->getOperand(Idx1).setReg(Reg2);
[all...] |
| AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
86 unsigned Group2 = GetGroup(Reg2);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 739 unsigned Reg2 = CSI[idx + 1].getReg();
761 assert(AArch64::GPR64RegClass.contains(Reg2) &&
769 assert(AArch64::FPR64RegClass.contains(Reg2) &&
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const {
77 return contains(Reg1) && contains(Reg2);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 662 unsigned Reg2 = MI->getOperand(2).getReg();
665 || !isARMLowRegister(Reg2))
667 if (Reg0 != Reg2) {
697 unsigned Reg2 = MI->getOperand(2).getReg();
698 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
[all...] |
| A15SDOptimizer.cpp | 89 unsigned Reg1, unsigned Reg2);
469 unsigned Reg1, unsigned Reg2) {
477 .addReg(Reg2)
|
| ARMFastISel.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 100 bool contains(unsigned Reg1, unsigned Reg2) const {
101 return MC->contains(Reg1, Reg2);
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXSwapRemoval.cpp | 838 unsigned Reg2 = MI->getOperand(2).getReg();
839 MI->getOperand(1).setReg(Reg2);
[all...] |
| PPCInstrInfo.cpp | 350 unsigned Reg2 = MI->getOperand(2).getReg();
378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
382 .addReg(Reg2, getKillRegState(Reg2IsKill))
389 MI->getOperand(0).setReg(Reg2);
393 MI->getOperand(1).setReg(Reg2);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
