| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.cpp | 131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
134 SmallBitVector Coverage(RegSize, false);
143 SmallBitVector Intersection(RegSize, false);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
216 (RegSize != 64 && (Imm >> RegSize != 0 || Imm == ~0U)))
220 unsigned Size = RegSize;
274 static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
276 return processLogicalImmediate(imm, regSize, encoding);
281 static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
283 bool res = processLogicalImmediate(imm, regSize, encoding);
291 /// integer value it represents with regSize bits.
292 static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
82 unsigned getSize() const { return RegSize; }
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 62 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
64 unsigned MFLoOpc, unsigned RegSize);
181 unsigned RegSize) {
189 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
200 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
206 unsigned RegSize) {
214 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
224 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 632 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
633 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
634 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
636 explicit operator bool() const { return RegSize; }
638 unsigned RegSize, ImmLSB, ImmSize;
728 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
730 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
732 if (And.RegSize == 64) {
[all...] |
| /external/clang/include/clang/Basic/ |
| TargetInfo.h | 652 /// variable size passed in RegSize.
654 unsigned RegSize,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 149 int RegSize;
152 RegSize = 8;
156 RegSize = 4;
169 count += RegSize;
[all...] |
| /external/clang/lib/CodeGen/ |
| TargetInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 663 unsigned RegSize = RegisterVT.getSizeInBits();
667 if (NumZeroBits == RegSize) {
679 if (NumSignBits == RegSize)
681 else if (NumZeroBits >= RegSize-1)
683 else if (NumSignBits > RegSize-8)
685 else if (NumZeroBits >= RegSize-8)
687 else if (NumSignBits > RegSize-16)
689 else if (NumZeroBits >= RegSize-16)
691 else if (NumSignBits > RegSize-32)
693 else if (NumZeroBits >= RegSize-32
[all...] |
| /external/clang/lib/Basic/ |
| Targets.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
