| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 330 /// in the set, or Regs.size() if they are all allocated.
331 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
332 for (unsigned i = 0; i < Regs.size(); ++i)
333 if (!isAllocated(Regs[i]))
335 return Regs.size();
358 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
359 unsigned FirstUnalloc = getFirstUnallocated(Regs);
360 if (FirstUnalloc == Regs.size())
364 unsigned Reg = Regs[FirstUnalloc];
372 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired)
[all...] |
| RegisterPressure.h | 202 SparseSet<unsigned> Regs;
223 return Regs.count(SparseIndex);
228 return Regs.insert(SparseIndex).second;
233 return Regs.erase(SparseIndex);
237 return Regs.size();
242 for (unsigned I : Regs) {
320 void addLiveRegs(ArrayRef<unsigned> Regs);
444 void increaseRegPressure(ArrayRef<unsigned> Regs);
445 void decreaseRegPressure(ArrayRef<unsigned> Regs);
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 50 const unsigned *Regs, unsigned Size) {
52 RegNo = Regs[RegNo];
228 const unsigned *Regs) {
232 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
238 const unsigned *Regs) {
242 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
248 const unsigned *Regs) {
253 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
255 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
260 const unsigned *Regs) {
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMUnwindOpAsm.cpp | 106 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) {
107 while (Regs) {
109 auto RangeMSB = 32 - countLeadingZeros(Regs);
110 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
120 Regs &= ~(-1u << RangeLSB);
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 56 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
59 const std::deque<CodeGenRegister> &Regs,
76 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
183 const CodeGenRegister::Vec &Regs = RC.getMembers();
184 if (Regs.empty())
189 OS << " {" << (*Regs.begin())->getWeight(RegBank)
321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
328 for (auto &RE : Regs) {
347 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
395 for (auto &RE : Regs) {
[all...] |
| CodeGenRegisters.cpp | 160 RegUnitIterator(const CodeGenRegister::Vec &Regs):
161 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
344 // SR is composed of multiple sub-regs. Find their names in this register.
[all...] |
| CodeGenTarget.cpp | 235 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
236 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
237 if (I == Regs.end())
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.cpp | 90 static const unsigned Regs[2][2] = {
95 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 367 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
371 RegisterGroup Group, const unsigned *Regs,
376 const unsigned *Regs, RegisterKind RegKind);
379 MemoryKind MemKind, const unsigned *Regs,
534 // Parse a register of group Group. If Regs is nonnull, use it to map
541 const unsigned *Regs, bool IsAddress) {
546 if (Regs && Regs[Reg.Num] == 0)
550 if (Regs)
551 Reg.Num = Regs[Reg.Num]
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 648 SmallVector<LiveReg, 4> Regs;
660 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
664 Regs.insert(i, LR);
668 Regs.push_back(LR);
674 while (!Regs.empty()) {
676 dv = Regs.pop_back_val().Value;
683 DomainValue *Latest = Regs.pop_back_val().Value;
|
| AggressiveAntiDepBreaker.h | 94 std::vector<unsigned> &Regs,
|
| AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs,
75 Regs.push_back(Reg);
149 // Examine the live-in regs of all successors.
544 std::vector<unsigned> Regs;
545 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
546 assert(Regs.size() > 0 && "Empty register group!");
547 if (Regs.size() == 0)
557 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
558 unsigned Reg = Regs[i];
562 // If Reg has any references, then collect possible rename regs
[all...] |
| CallingConvLower.cpp | 193 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
222 Regs.push_back(MCPhysReg(Locs[I].getLocReg()));
|
| RegisterPressure.cpp | 166 Regs.setUniverse(NumRegUnits + NumVirtRegs);
171 Regs.clear();
484 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) {
485 for (unsigned Reg : Regs) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 140 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs);
144 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) const;
534 /// Return the first register of class \p RegClass that is not in \p Regs.
566 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
568 for (const std::pair<unsigned, bool> &R : Regs)
575 /// Regs as the register operands that would be loaded / stored. It returns
580 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) {
581 unsigned NumRegs = Regs.size();
595 if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {
636 NewBase = Regs[NumRegs-1].first
[all...] |
| ARMFrameLowering.cpp | [all...] |
| Thumb2SizeReduction.cpp | 221 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
222 if (*Regs == ARM::CPSR)
663 // Early exit if the regs aren't all low regs.
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DbgValueHistoryCalculator.cpp | 171 BitVector &Regs) {
179 applyToClobberedRegisters(MI, TRI, [&](unsigned r) { Regs.set(r); });
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenInsert.cpp | 961 RegisterSet Regs[2];
964 Regs[S].insert(VR);
966 while (!Regs[S].empty()) {
969 Regs[OtherS].clear();
970 for (unsigned R = Regs[S].find_first(); R; R = Regs[S].find_next(R)) {
971 Regs[S].remove(R);
[all...] |
| HexagonFrameLowering.cpp | 688 // Split the double regs into subregs, and generate appropriate
690 // The only reason, we are split double regs is, llvm-mc does not
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 668 SDValue Regs[2];
669 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) &&
670 Regs[0].getNode() && Regs[1].getNode()) {
672 Base = Regs[I];
673 Index = Regs[1 - I];
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 899 SmallPtrSetImpl<const SCEV *> &Regs,
912 SmallPtrSetImpl<const SCEV *> &Regs,
916 SmallPtrSetImpl<const SCEV *> &Regs,
926 SmallPtrSetImpl<const SCEV *> &Regs,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| m88k.h | 65 #define REGs 32
90 /* Not applicable, instruction doesn't write to regs. */
208 Regs[REGs],
210 time_left[REGs],
212 wb_pri[REGs],
213 /* Integer unit control regs. */
214 SFU0_regs[REGs],
215 /* Floating point control regs. */
216 SFU1_regs[REGs],
[all...] |
