/external/llvm/lib/Target/Mips/ |
MipsAnalyzeImmediate.cpp | 45 AddInstr(SeqLs, Inst(SLL, Shamt)); 80 // Replace a ADDiu & SLL pair with a LUi. 83 // SLL 18 87 // Check if the first two instructions are ADDiu and SLL and the shift amount 90 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) 133 SLL = Mips::SLL; 138 SLL = Mips::DSLL;
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MipsAnalyzeImmediate.h | 43 /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to 50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. 58 unsigned ADDiu, ORi, SLL, LUi;
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MipsFastISel.cpp | [all...] |
MipsISelLowering.cpp | [all...] |
/external/pcre/dist/sljit/ |
sljitNativeSPARC_32.c | 59 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst))); 70 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst))); 92 FAIL_IF(push_inst(compiler, SLL | D(TMP_REG1) | S1(TMP_REG1) | IMM(1), DR(TMP_REG1))); 126 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
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sljitNativeMIPS_32.c | 90 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(24), DR(dst))); 108 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(16), DR(dst))); 147 FAIL_IF(push_inst(compiler, SLL | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS)); 192 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 195 return push_inst(compiler, SLL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 268 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 328 EMIT_SHIFT(SLL, SLLV);
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sljitNativeMIPS_64.c | 208 return push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(0), DR(dst)); 239 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL, SLL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS)); 284 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 287 return push_inst(compiler, SELECT_OP(DSRL32, SLL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 360 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 423 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV);
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sljitNativeSPARC_common.c | 150 #define SLL (OPC1(0x2) | OPC3(0x25)) 170 #define SLL_W SLL [all...] |
sljitNativeMIPS_common.c | 165 #define SLL (HI(0) | LO(0)) 189 #define SLL_W SLL [all...] |
/external/clang/test/CodeGen/ |
xcore-stringtype.c | 29 // CHECK: ul,sl,sll,ull,sll,ft,d,ld)"} 33 long long LL, unsigned long long ULL, signed long long SLL,
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/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.cpp | 397 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break; 508 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; 540 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; [all...] |
MIPS64Assembler.cpp | 386 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break; 509 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; 536 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break; [all...] |
MIPSAssembler.h | 314 void SLL(int Rd, int Rt, int shft);
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/external/v8/src/mips/ |
assembler-mips-inl.h | 439 Instr nop = SPECIAL | SLL; 452 Instr nop = SPECIAL | SLL;
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constants-mips.h | 411 SLL = ((0U << 3) + 0), 854 // A nop instruction. (Encoding of sll 0 0 0). 927 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) | [all...] |
/external/v8/src/mips64/ |
assembler-mips64-inl.h | 421 Instr nop = SPECIAL | SLL; 434 Instr nop = SPECIAL | SLL;
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constants-mips64.h | 394 SLL = ((0U << 3) + 0), 887 // A nop instruction. (Encoding of sll 0 0 0). 963 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) | [all...] |
/external/valgrind/none/tests/mips64/ |
shift_instructions.c | 9 ROTR, ROTRV, SLL, SLLV, 159 case SLL: 160 TEST2("sll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1); 161 TEST2("sll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3); 162 TEST2("sll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1); 163 TEST2("sll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1); 164 TEST2("sll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1); 165 TEST2("sll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3); 166 TEST2("sll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1); 167 TEST2("sll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1) [all...] |
/toolchain/binutils/binutils-2.25/include/opcode/ |
nios2r1.h | 431 #define MATCH_R1_SLL MATCH_R1_OPX0 (SLL)
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsMCCodeEmitter.cpp | 176 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 179 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
nds32-dis.c | 560 case ALU1 (SLL):
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/external/clang/lib/Sema/ |
SemaOverload.cpp | [all...] |
/external/v8/src/s390/ |
constants-s390.h | [all...] |
simulator-s390.h | 590 EVALUATE(SLL);
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/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | [all...] |