| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 97 unsigned Src0 = MI.getOperand(1).getReg();
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
152 .addReg(Src0)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 214 unsigned Src0 = 0, SubReg0;
220 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
222 if (Src0)
226 if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0))
307 unsigned Src0 = 0, SubReg0;
313 Src0 = getSrcFromCopy(&*Def, MRI, SubReg0);
316 if (Src0 && MRI->hasOneNonDBGUse(OrigSrc0)) {
317 assert(Src0 && "Can't delete copy w/o a valid original source!");
337 if (!Src0) {
339 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass)
[all...] |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 108 MI.getOperand(1).getReg(), // src0
222 unsigned Src0 = BMI->getOperand(
223 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
228 (void) Src0;
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
274 unsigned Src0 = MI.getOperand(
275 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
287 Src0 = TRI.getSubReg(Src0, SubRegIndex)
[all...] |
| SIShrinkInstructions.cpp | 119 // We don't need to check src0, all input types are legal, so just make sure
120 // src0 isn't using any modifiers.
147 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
148 MachineOperand &Src0 = MI.getOperand(Src0Idx);
150 // Only one literal constant is allowed per instruction, so if src0 is a
152 if (Src0.isImm() &&
153 TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx)))
156 // Literal constants and SGPRs can only be used in Src0, so if Src0 is an
159 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)
[all...] |
| SIInstrInfo.cpp | 834 unsigned Src0 = MI->getOperand(1).getReg();
839 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
843 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
897 AMDGPU::OpName::src0);
898 MachineOperand &Src0 = MI->getOperand(Src0Idx);
899 if (!Src0.isReg())
916 // For VOP2 instructions, any operand type is valid to use for src0. Make
917 // sure we can use the src1 as src0.
923 if (!isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0))
952 unsigned Reg = Src0.getReg()
[all...] |
| R600InstrInfo.cpp | 76 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
260 AMDGPU::OpName::src0,
271 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
324 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
553 //Todo : support shared src0 - src1 operand
[all...] |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_IDCT_s.h | 671 Src0 EQU 7
681 qXj0 QN Src0.S16
691 dXj0lo DN (Src0*2).S16
692 dXj0hi DN (Src0*2+1).S16
884 XTR5 EQU Src0
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_IDCT_s.h | 677 Src0 EQU 7
687 qXj0 QN Src0.S16
697 dXj0lo DN (Src0*2).S16
698 dXj0hi DN (Src0*2+1).S16
890 XTR5 EQU Src0
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
