/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
bitfield-bfm.s | 50 .macro op_bfm signed, reg, immr, imms 51 \signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15 55 op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms 60 op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms 66 op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)" 68 op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)" 75 op_bfm signed=\signed, reg=\reg, immr="((32-\lsb)&31)", imms="(\width-1)" 77 op_bfm signed=\signed, reg=\reg, immr="((64-\lsb)&63)", imms="(\width-1)" 83 op_bfm signed=\signed, reg=\reg, immr=\lsb, imms="(\lsb+\width-1)"
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/system/core/libpixelflinger/codeflinger/ |
Arm64Assembler.cpp | [all...] |
Arm64Assembler.h | 236 uint32_t immr, uint32_t imms); 238 uint32_t immr, uint32_t imms); 240 uint32_t immr, uint32_t imms);
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/external/v8/src/arm64/ |
assembler-arm64-inl.h | 1047 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) { 1048 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) || 1049 ((reg_size == kWRegSizeInBits) && is_uint5(immr))); 1051 DCHECK(is_uint6(immr)); 1052 return immr << ImmR_offset; 1065 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) { 1067 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(immr)) || 1068 ((reg_size == kWRegSizeInBits) && is_uint5(immr))); 1070 return immr << ImmRotate_offset [all...] |
assembler-arm64.h | [all...] |
assembler-arm64.cc | [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
aarch64-dis.c | 565 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. 728 /* value is N:immr:imms. */ 1557 int64_t immr, imms; local 1584 int64_t immr, imms, val; local 1611 int64_t immr = inst->operands[2].imm.value; local [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | 112 int64_t immr = Op2.getImm(); local 114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { 118 ((imms + 1 == immr))) { 123 shift = immr; 126 shift = immr; 129 shift = immr; 132 shift = immr; 162 int ImmR = MI->getOperand(3).getImm(); 166 (ImmR == 0 || ImmS < ImmR)) { [all...] |
/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64AddressingModes.h | 212 /// the form N:immr:imms. 251 // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n 255 unsigned Immr = (Size - I) & (Size - 1); 268 Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); 290 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the 293 // Extract the N, imms, and immr fields. 295 unsigned immr = (val >> 6) & 0x3f; local 302 unsigned R = immr & (size - 1); 318 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits [all...] |
/external/vixl/src/vixl/a64/ |
assembler-a64.h | [all...] |
macro-assembler-a64.h | [all...] |
assembler-a64.cc | 1089 unsigned immr, 1094 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); 1100 unsigned immr, 1105 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); 1111 unsigned immr, 1116 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelDAGToDAG.cpp | 1612 int immr = Srl_imm - Shl_imm; local [all...] |
/external/valgrind/VEX/priv/ |
guest_arm64_toIR.c | [all...] |