| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| bitfield-bfm.s | 50 .macro op_bfm signed, reg, immr, imms
51 \signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15
54 .macro ext2bfm signed, reg, imms
55 op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms
59 .macro sr2bfm signed, reg, shift, imms
60 op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms
66 op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)"
68 op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)
[all...] |
| /packages/apps/Settings/src/com/android/settings/inputmethod/ |
| InputMethodSettingValuesWrapper.java | 85 final List<InputMethodInfo> imms = mImm.getInputMethodList(); local
86 mMethodList.addAll(imms);
87 for (InputMethodInfo imi : imms) {
|
| /art/compiler/utils/ |
| assembler_test.h | 150 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
154 for (int64_t imm : imms) {
199 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
201 WarnOnCombinations(reg1_registers.size() * reg2_registers.size() * imms.size());
206 for (int64_t imm : imms) {
250 std::vector<int64_t> imms = CreateImmediateValuesBits(abs(imm_bits), (imm_bits > 0)); local
253 for (int64_t imm : imms) {
396 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes, as_uint); local
398 WarnOnCombinations(imms.size());
400 for (int64_t imm : imms) {
779 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); local
874 std::vector<int64_t> imms = CreateImmediateValues(imm_bytes); local
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_build_util.cpp | 47 memset(imms, 0, sizeof(imms));
59 while (imms[pos])
61 imms[pos] = imm;
358 while (imms[pos] && imms[pos]->reg.data.u32 != u)
361 ImmediateValue *imm = imms[pos];
|
| nv50_ir_build_util.h | 182 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; member in class:nv50_ir::BuildUtil
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 212 /// the form N:immr:imms.
290 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
293 // Extract the N, imms, and immr fields.
296 unsigned imms = val & 0x3f; local
299 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
303 unsigned S = imms & (size - 1);
318 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
322 // Extract the N and imms fields needed for checking
324 unsigned imms = val & 0x3f; local
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | [all...] |
| Arm64Assembler.h | 236 uint32_t immr, uint32_t imms);
238 uint32_t immr, uint32_t imms);
240 uint32_t immr, uint32_t imms);
|
| /external/mesa3d/src/gallium/auxiliary/translate/ |
| translate_sse.c | 455 unsigned imms[2] = {0, 0x3f800000}; local
658 x86_mov_imm(p->func, dst, imms[swizzle[0] - UTIL_FORMAT_SWIZZLE_0]);
668 x86_mov_imm(p->func, x86_make_disp(dst, 4), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]);
686 x86_mov_imm(p->func, x86_make_disp(dst, 8), imms[swizzle[2] - UTIL_FORMAT_SWIZZLE_0]);
696 x86_mov_imm(p->func, x86_make_disp(dst, 12), imms[swizzle[3] - UTIL_FORMAT_SWIZZLE_0]);
714 unsigned imms[2] = {0, 1}; local
773 imms[1] = (output_desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) ? 0xffff : 0x7ffff;
797 x86_mov16_imm(p->func, x86_make_disp(dst, 2), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]);
803 x86_mov_imm(p->func, dst, (imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0] << 16) | imms[swizzle[0] - UTIL_FORMAT_SWIZZLE_0])
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis.c | 565 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
728 /* value is N:immr:imms. */
1521 int64_t imms, val; local
1557 int64_t immr, imms; local
1584 int64_t immr, imms, val; local
1612 int64_t imms = inst->operands[3].imm.value; local
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 113 int64_t imms = Op3.getImm(); local
114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
116 shift = 31 - imms;
117 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
118 ((imms + 1 == immr))) {
120 shift = 63 - imms;
121 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
124 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
127 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f)
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1039 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
1040 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1041 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1043 return imms << ImmS_offset;
1056 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
1058 DCHECK(is_uint6(imms));
1059 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
1061 return imms << ImmSetBits_offset;
[all...] |
| assembler-arm64.h | [all...] |
| assembler-arm64.cc | [all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-i386-intel.c | 769 i.op[this_operand].imms = expP;
843 if (i386_finalize_immediate (exp_seg, i.op[0].imms,
849 i.op[this_operand].imms = expP;
996 i.op[this_operand].imms = expP;
|
| tc-i386.c | 248 expressionS *imms; member in union:i386_op
[all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.h | [all...] |
| macro-assembler-a64.h | [all...] |
| assembler-a64.cc | 1090 unsigned imms) {
1094 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1101 unsigned imms) {
1105 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1112 unsigned imms) {
1116 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd));
1127 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.size()) | Rn(rn) | Rd(rd))
[all...] |
| /frameworks/base/services/core/java/com/android/server/ |
| InputMethodManagerService.java | 747 MethodCallback(InputMethodManagerService imms, IInputMethod method,
749 mParentIMMS = imms;
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | [all...] |
