| /frameworks/compile/mclinker/lib/Target/AArch64/ |
| AArch64InsnHelpers.h | 25 static unsigned getBits(InsnType insn, int pos, int l) {
26 return (insn >> pos) & ((1 << l) - 1);
29 static unsigned getRt(InsnType insn) {
30 return getBits(insn, 0, 5);
33 static unsigned getRt2(InsnType insn) {
34 return getBits(insn, 10, 5);
37 static unsigned getRa(InsnType insn) {
38 return getBits(insn, 10, 5);
41 static unsigned getRd(InsnType insn) {
42 return getBits(insn, 0, 5)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| itbl-mips.h | 33 #define MIPS_IS_COP_INSN(insn) ((MIPS_OPCODE_COP0&(insn>>25)) \
35 #define MIPS_DECODE_COP_NUM(insn) ((~MIPS_OPCODE_COP0&(insn>>25))>>1)
36 #define MIPS_DECODE_COP_COFUN(insn) ((~MIPS_ENCODE_COP_NUM(3))&(insn))
39 #define ITBL_IS_INSN(insn) MIPS_IS_COP_INSN(insn)
40 #define ITBL_DECODE_PNUM(insn) MIPS_DECODE_COP_NUM(insn)
[all...] |
| tc-mt.c | 36 const CGEN_INSN * insn; member in struct:__anon75216
199 mt_insn insn;
205 insn.insn = mt_cgen_assemble_insn
206 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
208 if (!insn.insn)
215 gas_cgen_finish_insn (insn.insn, insn.buffer
197 mt_insn insn; local
464 const CGEN_INSN *insn = NULL; local
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.cpp | 192 * @param insn - The instruction with the reader function to use. The cursor
198 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) {
199 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor);
202 ++(insn->readerCursor);
210 * @param insn - See consumeByte().
214 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) {
215 return insn->reader(insn->readerArg, byte, insn->readerCursor)
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| spu.h | 90 #define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
91 #define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
93 #define DECODE_INSN_RT(insn) (insn & 0x7f)
94 #define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
95 #define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f
[all...] |
| /external/valgrind/none/tests/s390x/ |
| fpext.c | 7 #define L2F(insn, initial, target,round) \
11 asm volatile(insn(round,0,0,2) :"=f" (_t):"d"(source)); \
15 #define F2L(insn, initial, type, round, cc) \
19 asm volatile(insn(round,0,2,0) \
27 #define DO_INSN_L2F32(insn, round) \
30 printf(#insn " %f\n", L2F(insn, 0, f32, round)); \
31 printf(#insn " %f\n", L2F(insn, 1, f32, round)); \
32 printf(#insn " %f\n", L2F(insn, 0xffffffffUL, f32, round));
[all...] |
| comp-1.c | 21 #define SCOMP_REG_REG(insn, v1, v2) \
26 asm volatile( #insn " %1, %2\n\t" \
33 #insn, op1, op2, cc); \
38 #define SCOMP_REG_MEM(insn, v1, v2, op2_t) \
43 asm volatile( #insn " %1, %2\n\t" \
50 #insn, op1, (int64_t)op2, cc); \
55 #define SCOMP_REG_IMM(insn, v1, v2) \
59 asm volatile( insn(8, v2) \
66 #insn, op1, (int64_t)v2, cc); \
69 /* Run a sequence of signed comparisons for a given insn */
[all...] |
| fpconv.c | 12 We do not test rounding here. Just making sure the insn selector
13 picks the correct insn.
16 #define I2F(insn, initial, target_type) \
20 asm volatile(insn " %0,%1\n\t" :"=f" (target) :"d"(source)); \
21 printf(insn " %"PRId64" -> %f\n", source, target); \
24 #define DO_INSN_I32_TO_F(insn, target_type) \
27 I2F(insn, 0, target_type); \
28 I2F(insn, 1, target_type); \
29 I2F(insn, -1, target_type); \
30 I2F(insn, 42, target_type);
[all...] |
| comp-2.c | 21 #define SCOMP_REG_REG(insn, v1, v2) \
26 asm volatile( #insn " %1, %2\n\t" \
33 #insn, op1, op2, cc); \
38 #define SCOMP_REG_MEM(insn, v1, v2, op2_t) \
43 asm volatile( #insn " %1, %2\n\t" \
50 #insn, op1, (uint64_t)op2, cc); \
55 #define SCOMP_REG_IMM(insn, v1, v2) \
59 asm volatile( insn(8, v2) \
66 #insn, op1, (uint64_t)v2, cc); \
69 /* Run a sequence of unsigned comparisons for a given insn */
[all...] |
| condloadstore.c | 5 #define LOAD_REG_MEM(insn, s, ccset, initial, mask) \
19 insn(1,mask,5,000,00) \
23 printf(#insn " %16.16lX into %16.16lX if mask" \
29 #define LOAD_REG_REG(insn, s, ccset, initial, mask) \
42 insn(mask,1,2) \
46 printf(#insn " %16.16lX into %16.16lX if mask" \
51 #define STORE_REG_REG(insn, s, ccset, initial, mask) \
65 insn(1,mask,5,000,00) \
69 printf(#insn " %16.16lX into %16.16lX if mask" \
75 #define INSNVALCCINIT(insn, value, ccset, INIT, FUNC)
[all...] |
| /external/libpcap/ |
| bpf_dump.c | 32 const struct bpf_insn *insn; local
36 insn = p->bf_insns;
39 for (i = 0; i < n; ++insn, ++i) {
40 printf("%u %u %u %u\n", insn->code,
41 insn->jt, insn->jf, insn->k);
46 for (i = 0; i < n; ++insn, ++i)
48 insn->code, insn->jt, insn->jf, insn->k)
[all...] |
| /external/tcpdump/ |
| bpf_dump.c | 36 struct bpf_insn *insn; local
40 insn = p->bf_insns;
43 for (i = 0; i < n; ++insn, ++i) {
44 printf("%u %u %u %u\n", insn->code,
45 insn->jt, insn->jf, insn->k);
50 for (i = 0; i < n; ++insn, ++i)
52 insn->code, insn->jt, insn->jf, insn->k)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/s390/ |
| esa-operands.s | 3 .insn e,0x0101
4 .insn ri,0xa70a0000,%r1,-32767
5 .insn rr,0x1800,%r1,%r2
6 .insn rre,0xb25e0000,%r1,%r2
7 .insn rrf,0xb35b0000,%f1,%f2,9,%f3
8 .insn rs,0xba000000,%r1,%r2,3(%r4)
9 .insn rsi,0x84000000,%r1,%r2,test_rsi
10 .insn rx,0x58000000,%r1,2(%r3,%r4)
11 .insn rxe,0xed000000001a,%f1,2(%r3)
12 .insn rxf,0xed000000001e,%f1,%f2,3(%r4,%r5
[all...] |
| zarch-operands.s | 3 .insn rie,0xec0000000045,%r1,%r2,test_rie
4 .insn ril,0xc00500000000,%r14,test_ril
5 .insn rse,0xeb000000000d,%r1,%r2,3(%r4)
6 .insn ssf,0xc80000000000,1(%r2),3(%r4),%r5
|
| /external/google-breakpad/src/third_party/libdisasm/ |
| x86_insn.c | 11 int x86_insn_is_valid( x86_insn_t *insn ) {
12 if ( insn && insn->type != insn_invalid && insn->size > 0 ) {
19 uint32_t x86_get_address( x86_insn_t *insn ) {
21 if (! insn || ! insn->operands ) {
25 for (op_lst = insn->operands; op_lst; op_lst = op_lst->next ) {
40 int32_t x86_get_rel_offset( x86_insn_t *insn ) {
42 if (! insn || ! insn->operands )
[all...] |
| ia32_implicit.h | 11 unsigned int ia32_insn_implicit_ops( x86_insn_t *insn, unsigned int impl_idx );
|
| x86_operand_list.h | 6 x86_op_t * x86_operand_new( x86_insn_t *insn );
|
| x86_operand_list.c | 5 static void x86_oplist_append( x86_insn_t *insn, x86_oplist_t *op ) {
8 if (! insn ) {
12 list = insn->operands;
14 insn->operand_count = 1;
20 insn->explicit_count = 1;
21 insn->operands = op;
29 insn->operand_count = insn->operand_count + 1;
30 insn->explicit_count = insn->explicit_count + 1
[all...] |
| ia32_insn.c | 47 /* these are not used in stack insn */
55 /* determine what this insn does to the stack */
56 static void ia32_stack_mod(x86_insn_t *insn) {
59 if (! insn || ! insn->operands ) {
63 dest = &insn->operands->op;
65 src = &insn->operands->next->op;
68 insn->stack_mod = 0;
69 insn->stack_mod_val = 0;
71 switch ( insn->type )
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/rawdex/formats/ |
| ContainsTarget.java | 26 public long getTarget(Instruction insn);
28 public void setTarget(Instruction insn, long target);
|
| Format22b.java | 26 public void writeToFile(DexRandomAccessFile file, Instruction insn) throws IOException {
27 file.writeByte((byte) insn.info.value);
28 file.writeByte((byte) insn.vregA);
29 file.writeByte((byte) insn.vregB);
30 file.writeByte((byte) insn.vregC);
50 public long getConst(Instruction insn) {
51 return insn.vregC;
55 public void setConst(Instruction insn, long constant) {
56 insn.vregC = constant;
|
| /dalvik/dx/src/com/android/dx/dex/code/form/ |
| Form30t.java | 42 public String insnArgString(DalvInsn insn) {
43 return branchString(insn);
48 public String insnCommentString(DalvInsn insn, boolean noteIndices) {
49 return branchComment(insn);
60 public boolean isCompatible(DalvInsn insn) {
61 if (!((insn instanceof TargetInsn) &&
62 (insn.getRegisters().size() == 0))) {
71 public boolean branchFits(TargetInsn insn) {
77 public void writeTo(AnnotatedOutput out, DalvInsn insn) {
78 int offset = ((TargetInsn) insn).getTargetOffset()
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/form/ |
| Form30t.java | 42 public String insnArgString(DalvInsn insn) {
43 return branchString(insn);
48 public String insnCommentString(DalvInsn insn, boolean noteIndices) {
49 return branchComment(insn);
60 public boolean isCompatible(DalvInsn insn) {
61 if (!((insn instanceof TargetInsn) &&
62 (insn.getRegisters().size() == 0))) {
71 public boolean branchFits(TargetInsn insn) {
77 public void writeTo(AnnotatedOutput out, DalvInsn insn) {
78 int offset = ((TargetInsn) insn).getTargetOffset()
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| disassem.c | 62 * insn[cc][mod] [operands]
292 static void disasm_register_shift(const disasm_interface_t *di, u_int insn);
293 static void disasm_print_reglist(const disasm_interface_t *di, u_int insn);
294 static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn,
296 static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn,
298 static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn,
307 u_int insn = di->di_readword(loc); local
313 /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
316 if ((insn & i_ptr->mask) == i_ptr->pattern)
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/form/ |
| Form21t.java | 43 public String insnArgString(DalvInsn insn) {
44 RegisterSpecList regs = insn.getRegisters();
45 return regs.get(0).regString() + ", " + branchString(insn);
50 public String insnCommentString(DalvInsn insn, boolean noteIndices) {
51 return branchComment(insn);
62 public boolean isCompatible(DalvInsn insn) {
63 RegisterSpecList regs = insn.getRegisters();
65 if (!((insn instanceof TargetInsn) &&
71 TargetInsn ti = (TargetInsn) insn;
77 public boolean branchFits(TargetInsn insn) {
[all...] |
