| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | [all...] |
| LoopStrengthReduce.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/lib/Renderscript/ |
| RSKernelExpand.cpp | 409 llvm::Value *Cond, *IVNext, *IV, *IVVar;
427 Cond = Builder.CreateICmpULT(LowerBound, UpperBound);
428 Builder.CreateCondBr(Cond, HeaderBB, AfterBB);
444 Cond = Builder.CreateICmpULT(IVNext, UpperBound);
445 Builder.CreateCondBr(Cond, HeaderBB, AfterBB);
[all...] |
| /external/clang/lib/CodeGen/ |
| CGStmtOpenMP.cpp | [all...] |
| /external/clang/lib/Sema/ |
| SemaTemplateInstantiateDecl.cpp | 173 Expr *Cond = nullptr;
179 Cond = Result.getAs<Expr>();
181 if (A->getCond()->isTypeDependent() && !Cond->isTypeDependent()) {
182 ExprResult Converted = S.PerformContextuallyConvertToBool(Cond);
185 Cond = Converted.get();
189 if (A->getCond()->isValueDependent() && !Cond->isValueDependent() &&
190 !Expr::isPotentialConstantExprUnevaluated(Cond, cast<FunctionDecl>(Tmpl),
199 EnableIfAttr(A->getLocation(), S.getASTContext(), Cond,
[all...] |
| SemaDeclAttr.cpp | 785 Expr *Cond = Attr.getArgAsExpr(0);
786 if (!Cond->isTypeDependent()) {
787 ExprResult Converted = S.PerformContextuallyConvertToBool(Cond);
790 Cond = Converted.get();
798 if (!Cond->isValueDependent() &&
799 !Expr::isPotentialConstantExprUnevaluated(Cond, cast<FunctionDecl>(D),
808 EnableIfAttr(Attr.getRange(), S.Context, Cond, Msg,
[all...] |
| SemaStmt.cpp | 583 Sema::ActOnStartOfSwitchStmt(SourceLocation SwitchLoc, Expr *Cond,
594 Cond = CondResult.get();
597 if (!Cond)
601 Expr *Cond;
604 SwitchConvertDiagnoser(Expr *Cond)
606 Cond(Cond) {}
616 << T << Cond->getSourceRange();
645 } SwitchDiagnoser(Cond);
648 PerformContextualImplicitConversion(SwitchLoc, Cond, SwitchDiagnoser)
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 153 const Value *Cond);
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 421 uint32_t Cond = (Insn >> 28) & 0xF;
422 if (Cond == 0xF)
424 if (Cond != 0xE)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 280 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
283 /// Cond[0] = Jump_c
284 /// Cond[1] = p
286 /// Cond[0] = ENDLOOP
287 /// Cond[1] = MBB
289 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
290 /// Cond[1] = R
291 /// Cond[2] = Imm
296 SmallVectorImpl<MachineOperand> &Cond,
300 Cond.clear()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 168 const Value *Cond);
266 const Value *Cond) {
267 if (!isa<ExtractValueInst>(Cond))
270 const auto *EV = cast<ExtractValueInst>(Cond);
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| GlobalOpt.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | 601 ICmpInst::Predicate Cond,
608 if (ICmpInst::isSigned(Cond))
627 return new ICmpInst(ICmpInst::getSignedPredicate(Cond), Offset,
645 return new ICmpInst(Cond, GEPLHS->getOperand(0), GEPRHS->getOperand(0));
671 Value *Cmp = Builder->CreateICmp(ICmpInst::getSignedPredicate(Cond),
684 ICmpInst::getSwappedPredicate(Cond), I);
688 return FoldGEPICmp(GEPLHS, GEPRHS->getOperand(0), Cond, I);
710 Builder->getInt1(ICmpInst::isTrueWhenEqual(Cond)));
716 return new ICmpInst(ICmpInst::getSignedPredicate(Cond), LHSV, RHSV);
727 return new ICmpInst(ICmpInst::getSignedPredicate(Cond), L, R)
[all...] |
| InstructionCombining.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | 287 SDValue Cond = GetScalarizedVector(N->getOperand(0));
301 if (Cond->getOpcode() == ISD::SETCC) {
302 EVT OpVT = Cond->getOperand(0)->getValueType(0);
310 EVT CondVT = Cond.getValueType();
318 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
319 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
325 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
326 Cond, DAG.getValueType(MVT::i1));
332 LHS.getValueType(), Cond, LHS,
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 58 AArch64CC::CondCode parseCondCodeString(StringRef Cond);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
570 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
572 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
577 True.getValueType(), True, FCC0, False, Cond);
[all...] |
| /external/llvm/lib/Transforms/Instrumentation/ |
| AddressSanitizer.cpp | 745 PHINode *createPHI(IRBuilder<> &IRB, Value *Cond, Value *ValueIfTrue,
[all...] |
| MemorySanitizer.cpp | [all...] |
