| /external/llvm/tools/llvm-dwp/ |
| llvm-dwp.cpp | 198 uint64_t Mask = Buckets.size() - 1;
201 auto H = S & Mask;
205 H += ((S >> 32) & Mask) | 1;
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| bitstream_io.cpp | 29 static const UChar Mask[ ] =
372 BitstreamPutBits(stream, restBits, Mask[restBits]);
400 BitstreamPutBits(stream,count,Mask[count]);
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| ipxrip.h | 27 UCHAR Mask[4];
|
| d3d10shader.h | 93 BYTE Mask;
|
| d3d11shader.h | 131 BYTE Mask;
|
| fltdefs.h | 105 PBYTE Mask;
|
| /external/llvm/include/llvm/ADT/ |
| SmallBitVector.h | 228 // Mask off previous bits.
307 uintptr_t Mask = EMask - IMask;
308 setSmallBits(getSmallBits() | Mask);
338 uintptr_t Mask = EMask - IMask;
339 setSmallBits(getSmallBits() & ~Mask);
517 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
518 /// This computes "*this |= Mask".
519 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) {
521 applyMask<true, false>(Mask, MaskWords);
523 getPointer()->setBitsInMask(Mask, MaskWords)
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitstreamReader.h | 347 static const unsigned Mask = sizeof(word_t) > 4 ? 0x3f : 0x1f;
353 // Use a mask to avoid undefined behavior.
354 CurWord >>= (NumBits & Mask);
371 // Use a mask to avoid undefined behavior.
372 CurWord >>= (BitsLeft & Mask);
|
| /external/llvm/include/llvm/Support/ |
| MathExtras.h | 53 T Mask = std::numeric_limits<T>::max() >> Shift;
55 if ((Val & Mask) == 0) {
60 Mask >>= Shift;
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 241 APInt Mask(APInt::getLowBitsSet(TypeWidth, TypeWidth - NumBits));
243 ConstantInt::get(BO->getContext(), Mask));
281 APInt Mask(APInt::getHighBitsSet(TypeWidth, TypeWidth - NumBits));
283 ConstantInt::get(BO->getContext(), Mask));
392 // The mask we constructed says what the trunc would do if occurring
395 // mask as appropriate.
437 Constant *Mask = ConstantInt::get(I.getContext(), Bits);
439 Mask = ConstantVector::getSplat(VT->getNumElements(), Mask);
440 return BinaryOperator::CreateAnd(X, Mask);
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_optimize.c | 40 unsigned int Mask;
113 && (rc_swizzle_to_writemask(src->Swizzle) & sc_data->Mask)) {
128 unsigned int mask)
134 sc_data.Mask = mask;
674 unsigned int mask)
677 if (rc_src_reads_dst_mask(file, mask, index,
689 unsigned int mask)
693 (mask & d->Writer->WriteMask)) {
|
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| RuntimeDyldChecker.cpp | 617 uint64_t Mask = ((uint64_t)1 << (HighBit - LowBit + 1)) - 1;
618 uint64_t SlicedValue = (SubExprResult.getValue() >> LowBit) & Mask;
[all...] |
| /external/llvm/lib/IR/ |
| Attributes.cpp | 578 uint64_t Mask = 0;
590 Mask |= (Log2_32(ASN->getAlignment()) + 1) << 16;
592 Mask |= (Log2_32(ASN->getStackAlignment()) + 1) << 26;
594 llvm_unreachable("dereferenceable not supported in bit mask");
596 Mask |= AttributeImpl::getAttrMask(Kind);
599 return Mask;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 112 // This should return a register mask that is the same as that returned by
671 unsigned Mask = (1 << NumBits) - 1;
672 if ((unsigned)Offset <= Mask * Scale)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 416 unsigned Mask = (0xFFFFFFFFU >> (32-NBits));
417 unsigned Val = (SO.getImm() & Mask) << Shift;
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 49 unsigned Mask = MI.getOperand(1).getImm();
52 if (Mask & 1)
55 if (Mask & 2)
58 if (Mask & 4)
61 if (Mask & 8)
64 if (Mask & 16)
67 if (Mask & 32)
[all...] |
| /external/llvm/tools/llvm-readobj/ |
| ARMEHABIPrinter.h | 33 uint8_t Mask;
63 void PrintRegisters(uint32_t Mask, StringRef Prefix);
295 if ((Opcodes[OCI ^ 3] & Ring[REI].Mask) == Ring[REI].Value) {
|
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 458 Constant *Mask = ConstantVector::get(Idxs);
460 Value *V = new ShuffleVectorInst(Val0, Val1, Mask, "Shuff",
|
| /external/vboot_reference/utility/ |
| efidecompress.c | 218 UINT16 Mask;
261 Mask = (UINT16) (1U << (15 - TableBits));
290 if (Index3 & Mask) {
334 UINT32 Mask;
340 Mask = 1U << (BITBUFSIZ - 1 - 8);
344 if (Sd->mBitBuf & Mask) {
350 Mask >>= 1;
397 UINT32 Mask;
422 Mask = 1U << (BITBUFSIZ - 1 - 3);
423 while (Mask & Sd->mBitBuf)
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| LiveIntervalAnalysis.cpp | 230 if (const uint32_t *Mask = MBB.getBeginClobberMask(TRI)) {
232 RegMaskBits.push_back(Mask);
245 if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
247 RegMaskBits.push_back(Mask);
250 // Compute the number of register mask instructions in this block.
747 // Compute a mask of lanes that are defined.
865 // Register mask functions
885 // We are going to enumerate all the register mask slots contained in LI.
900 // *SlotI overlaps LI. Collect mask bits.
907 // Remove usable registers clobbered by this mask
[all...] |
| MachineVerifier.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 512 // Instead, we load all significant words, mask bits off, and concatenate
734 SDValue Mask = Op.getOperand(0);
738 assert(VT.isVector() && !Mask.getValueType().isVector()
754 // Generate a mask operand.
757 // What is the size of each element in the vector mask.
760 Mask = DAG.getSelect(DL, BitTy, Mask,
765 // Broadcast the mask so that the entire vector is all-one or all zero.
766 SmallVector<SDValue, 8> Ops(NumElem, Mask);
767 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops)
[all...] |
| SelectionDAGBuilder.h | 198 uint64_t Mask;
203 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
205 Mask(mask), BB(bb), Bits(bits), ExtraProb(Prob) { }
207 CaseBits() : Mask(0), BB(nullptr), Bits(0) {}
276 Mask(M), ThisBB(T), TargetBB(Tr), ExtraProb(Prob) { }
277 uint64_t Mask;
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 224 uint64_t Mask = (1ULL << Size) - 1;
226 if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
234 uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
235 Imm &= Mask;
242 Imm |= ~Mask;
|
