/external/llvm/lib/Target/Hexagon/ |
HexagonStoreWidening.cpp | 450 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF); 451 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC);
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HexagonEarlyIfConv.cpp | 421 const TargetRegisterClass *RC = MRI->getRegClass(DefR); 422 if (RC == &Hexagon::PredRegsRegClass) 805 const TargetRegisterClass *RC = MRI->getRegClass(DR); 806 const MCInstrDesc &D = RC == &IntRegsRegClass ? TII->get(C2_mux) 813 unsigned MuxR = MRI->createVirtualRegister(RC); [all...] |
HexagonExpandCondsets.cpp | 664 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); 665 switch (RC->getSize()) { [all...] |
HexagonSplitDouble.cpp | 644 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg()); 645 unsigned NewR = MRI->createVirtualRegister(RC); [all...] |
HexagonVLIWPacketizer.cpp | 276 const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg); 277 if (RC == &Hexagon::PredRegsRegClass) 334 const TargetRegisterClass* RC) { 365 const TargetRegisterClass *RC) { 414 const TargetRegisterClass* RC) { 417 if (RC == &Hexagon::PredRegsRegClass) 721 const TargetRegisterClass* RC) { 753 if (RC == &Hexagon::PredRegsRegClass) 757 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI)) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEFrameLowering.cpp | 156 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 157 unsigned VR = MRI.createVirtualRegister(RC); 160 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); 171 const TargetRegisterClass *RC = RegInfo.intRegClass(4); 172 unsigned VR = MRI.createVirtualRegister(RC); 177 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); 189 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); 190 unsigned VR0 = MRI.createVirtualRegister(RC); 191 unsigned VR1 = MRI.createVirtualRegister(RC); 198 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0) [all...] |
MipsSEISelDAGToDAG.cpp | 141 const TargetRegisterClass *RC; 143 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 145 V0 = RegInfo.createVirtualRegister(RC); 146 V1 = RegInfo.createVirtualRegister(RC); 936 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); 939 CurDAG->getTargetConstant(RC->getID(), DL, [all...] |
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyPEI.cpp | 345 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); 362 unsigned Align = RC->getAlignment(); 369 FrameIdx = MFI->CreateStackObject(RC->getSize(), Align, true); 375 MFI->CreateFixedSpillStackObject(RC->getSize(), FixedSlot->Offset); 469 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 471 RC, TRI); 498 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 499 TII.loadRegFromStackSlot(*MBB, I, Reg, CSI[i].getFrameIdx(), RC, TRI); [all...] |
/external/clang/test/SemaCXX/ |
nested-name-spec.cpp | 71 struct RC; 77 struct A2::RC { 103 void f6(int A2::RC::x); // expected-error{{parameter declarator cannot be qualified}} 105 int A2::RC::x; // expected-error{{non-static data member defined out-of-line}}
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/external/llvm/include/llvm/CodeGen/ |
MachineRegisterInfo.h | 173 /// Returns true if liveness for register class @p RC should be tracked at 175 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const { 176 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; 562 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 565 /// register to be a common subclass of RC and the current register class, 572 const TargetRegisterClass *RC, [all...] |
/external/llvm/lib/CodeGen/ |
MachineInstr.cpp | [all...] |
MachineLICM.cpp | 820 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 822 RegClassWeight W = TRI->getRegClassWeight(RC); 836 const int *PS = TRI->getRegClassPressureSets(RC); [all...] |
MachineVerifier.cpp | [all...] |
PeepholeOptimizer.cpp | 526 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); 540 unsigned NewVR = MRI->createVirtualRegister(RC); [all...] |
ScheduleDAGInstrs.cpp | 369 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); 370 if (!RC.HasDisjunctSubRegs) 375 return RC.getLaneMask(); [all...] |
TargetInstrInfo.cpp | 342 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, 347 Size = RC->getSize(); 365 assert(RC->getSize() >= (Offset + Size) && "bad subregister range"); 368 Offset = RC->getSize() - (Offset + Size); 420 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 423 return RC->contains(LiveOp.getReg()) ? RC : nullptr; 425 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 426 return RC; 475 const TargetRegisterClass *RC [all...] |
TwoAddressInstructionPass.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGRRList.cpp | 291 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); 292 RegClass = RC->getID(); 300 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 301 RegClass = RC->getID(); 308 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); 309 RegClass = RC->getID(); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | 366 const TargetRegisterClass *RC = 368 if (!RC) 376 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || 377 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { 390 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || 391 AArch64::FPR32RegClass.hasSubClassEq(RC)) { 486 const TargetRegisterClass *RC = nullptr; 489 RC = &AArch64::GPR64RegClass; 493 RC = &AArch64::GPR32RegClass; 497 RC = &AArch64::FPR64RegClass [all...] |
/external/llvm/lib/Target/ARM/ |
ARMAsmPrinter.cpp | 348 unsigned RC; 349 InlineAsm::hasRegClassConstraint(Flags, RC); 350 if (RC == ARM::GPRPairRegClassID) { [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | 700 const TargetRegisterClass *RC = 702 if (!RC) 706 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && 707 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && 708 !PPC::G8RCRegClass.hasSubClassEq(RC) && 709 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) 735 const TargetRegisterClass *RC = 737 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 739 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || 740 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 645 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC, 653 return std::make_pair(Map[Index], RC); [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
alpha-opc.c | 79 /* The same for the RC field. */ 212 #define RC (RB + 1) 216 #define FA (RC + 1) 244 /* The RC field when it must be the same as the RB field. */ 248 /* The RC field when it can *default* to RA. */ 253 /* The RC field when it can *default* to RB. */ 421 #define ARG_OPRLZ1 { ZA, LIT, RC } 567 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ 568 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ 569 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo * [all...] |
/external/libavc/test/encoder/ |
main.c | 83 RC, 154 { "--", "--rc", RC, "Rate control mode 0: Constant Qp, 1: Storage, 2: CBR non low delay, 3: CBR low delay \n" }, 618 case RC: [all...] |