| /external/llvm/lib/Target/Mips/ |
| MipsConstantIslandPass.cpp | 347 const MipsSubtarget *STI;
369 IsPIC(TM.getRelocationModel() == Reloc::PIC_), STI(nullptr),
451 STI = &static_cast<const MipsSubtarget &>(mf.getSubtarget());
453 if (!STI->inMips16Mode() || !MipsSubtarget::useConstantIslands()) {
456 TII = (const Mips16InstrInfo *)STI->getInstrInfo();
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 72 const MCSubtargetInfo &STI);
89 const MCSubtargetInfo &STI) {
94 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
102 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
106 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
792 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
[all...] |
| X86InstrInfo.cpp | 104 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
105 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
107 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
110 Subtarget(STI), RI(STI.getTargetTriple()) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 88 const MCSubtargetInfo *STI;
108 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), *Reg.STI)));
303 const MCSubtargetInfo *STI,
308 Op->Reg.STI = STI;
383 AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
386 : MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser),
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 271 const ARMSubtarget *STI;
401 STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());
402 TII = STI->getInstrInfo();
490 if (isThumb2 && !STI->prefers32BitThumb())
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 775 MCSubtargetInfo &STI = copySTI();
777 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
779 STI.ToggleFeature(OldMode.flip(mode)));
782 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
805 X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
807 : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr) {
812 CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 358 MCSubtargetInfo &STI = copySTI();
359 FeatureBitset FeatureBits = STI.getFeatureBits();
361 STI.setFeatureBits(FeatureBits);
363 ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature)));
364 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
369 MCSubtargetInfo &STI = copySTI();
371 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
372 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
378 MCSubtargetInfo &STI = copySTI();
380 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)))
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 286 MCSubtargetInfo &STI = copySTI();
287 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
352 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
354 : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
361 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | 663 #define STI CHOICE(sti, sti, sti)
[all...] |
