| /external/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyTraverse.h | 474 void printSExpr(const SExpr *E, StreamType &SS, unsigned P, bool Sub=true) {
479 if (Sub && E->block() && E->opcode() != COP_Variable) {
792 bool Sub = false;
797 Sub = true;
802 self()->printSExpr(E, SS, Prec_MAX, Sub);
|
| /external/clang/lib/Frontend/ |
| CompilerInstance.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 128 Sub(Op.getSubReg()) {}
129 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
131 return Reg == RR.Reg && Sub == RR.Sub;
134 unsigned Reg, Sub;
140 unsigned getMaskForSub(unsigned Sub);
190 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
191 switch (Sub) {
220 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
234 unsigned Mask = getMaskForSub(RR.Sub) | Exec
[all...] |
| HexagonHardwareLoops.cpp | 297 unsigned Sub;
307 Contents.R.Sub = u;
321 return Contents.R.Sub;
329 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | [all...] |
| PPCInstrInfo.cpp | 246 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 254 Value *Sub = nullptr;
256 Sub = Builder->CreateSub(X, Y, "suba");
258 Sub = Builder->CreateSub(Builder->CreateNeg(C1), Y, "subc");
259 if (Sub)
261 BinaryOperator::CreateMul(Sub,
[all...] |
| /external/clang/lib/AST/ |
| ItaniumMangle.cpp | [all...] |
| /external/clang/lib/Lex/ |
| ModuleMap.cpp | 71 Module *Sub = lookupModuleQualified(Id[I].first, Context);
72 if (!Sub) {
81 Context = Sub;
535 if (Module *Sub = lookupModuleQualified(Name, Context))
536 return Sub;
553 if (Module *Sub = lookupModuleQualified(Name, Parent))
554 return std::make_pair(Sub, false);
[all...] |
| PPDirectives.cpp | 389 StringRef Sub = Directive.substr(2);
390 if (Sub.empty() || // "if"
391 Sub == "def" || // "ifdef"
392 Sub == "ndef") { // "ifndef"
401 StringRef Sub = Directive.substr(1);
402 if (Sub == "ndif") { // "endif"
422 } else if (Sub == "lse") { // "else".
449 } else if (Sub == "lif") { // "elif".
[all...] |
| /external/compiler-rt/lib/sanitizer_common/ |
| sanitizer_allocator.h | 221 void Sub(AllocatorStat i, uptr v) {
940 stats_.Sub(AllocatorStatAllocated, SizeClassMap::Size(class_id));
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | 323 case ISD::SUB: {
799 } else if (Addr.getOpcode() == ISD::SUB) {
800 // sub C, x -> add (sub 0, x), C
807 // XXX - This is kind of hacky. Create a dummy sub node so we can check
810 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
813 if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
867 } else if (Addr.getOpcode() == ISD::SUB) {
868 // sub C, x -> add (sub 0, x),
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 816 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 93 // The lane mask is simply the union of all sub-indices.
97 assert(M && "Missing lane mask, sub-register cycle?");
132 // sub-register.
230 // Map explicit sub-registers first, so the names take precedence.
231 // The inherited sub-registers are mapped below.
274 // We found a new name for the orphaned sub-register.
314 " has itself as a sub-register");
321 // Ensure that every sub-register has a unique name.
330 PrintFatalError(Loc, "Sub-register can't have two names: " +
335 // Derive possible names for sub-register concatenations from any explici
[all...] |
| /external/regex-re2/lib/codereview/ |
| codereview.py | 85 def Sub(l1, l2):
89 l = l1 + Sub(l2, l1)
548 who = re.sub('@.*', '', m.get('sender', ''))
549 text = re.sub("\n(.|\n)*", '', m.get('text', ''))
866 l = Sub(l, taken.keys())
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 157 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, SUB);
169 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, SUB);
176 void MacroAssembler::Sub(const Register& rd,
184 AddSubMacro(rd, rn, operand, LeaveFlags, SUB);
197 AddSubMacro(rd, rn, operand, SetFlags, SUB);
221 Sub(rd, AppropriateZeroRegFor(rd), operand);
1246 Sub(csp, StackPointer(), space);
[all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.cc | 794 // Add/sub extended supports shift <= 4. We want to support exactly the
[all...] |
| /frameworks/base/core/java/android/text/ |
| Html.java | 545 out.append("<sub>");
617 out.append("</sub>");
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | 513 return Ty->isFPOrFPVectorTy() ? Instruction::FSub : Instruction::Sub;
[all...] |
| /prebuilts/gdb/darwin-x86/include/python2.7/ |
| Python-ast.h | 18 typedef enum _operator { Add=1, Sub=2, Mult=3, Div=4, Mod=5, Pow=6, LShift=7,
|
| /prebuilts/gdb/linux-x86/include/python2.7/ |
| Python-ast.h | 18 typedef enum _operator { Add=1, Sub=2, Mult=3, Div=4, Mod=5, Pow=6, LShift=7,
|
| /prebuilts/python/darwin-x86/2.7.5/include/python2.7/ |
| Python-ast.h | 18 typedef enum _operator { Add=1, Sub=2, Mult=3, Div=4, Mod=5, Pow=6, LShift=7,
|
| /prebuilts/python/linux-x86/2.7.5/include/python2.7/ |
| Python-ast.h | 18 typedef enum _operator { Add=1, Sub=2, Mult=3, Div=4, Mod=5, Pow=6, LShift=7,
|
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 162 | Sub
249 | Sub
[all...] |
| /external/llvm/include/llvm/IR/ |
| Instructions.h | 699 Sub,
[all...] |
