| /prebuilts/ndk/current/platforms/android-19/arch-mips/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /prebuilts/ndk/current/platforms/android-21/arch-mips/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /prebuilts/ndk/current/platforms/android-21/arch-mips64/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /prebuilts/ndk/current/platforms/android-23/arch-mips/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /prebuilts/ndk/current/platforms/android-23/arch-mips64/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /prebuilts/ndk/current/platforms/android-24/arch-mips/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /prebuilts/ndk/current/platforms/android-24/arch-mips64/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /prebuilts/ndk/current/platforms/android-9/arch-mips/usr/include/machine/ |
| regnum.h | 38 #define V0 2
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 140 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
145 V0 = RegInfo.createVirtualRegister(RC);
152 // lui $v0, %hi(%neg(%gp_rel(fname)))
153 // daddu $v1, $v0, $t9
156 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
158 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
168 // lui $v0, %hi(__gnu_local_gp)
169 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
170 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
172 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
[all...] |
| MipsISelLowering.cpp | [all...] |
| /libcore/luni/src/test/java/libcore/java/lang/ |
| ClassCastExceptionTest.java | 81 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
86 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
|
| /external/clang/test/Parser/ |
| MicrosoftExtensions.cpp | 310 __declspec(property) int V0; // expected-error {{expected '(' after 'property'}}
|
| /external/libgdx/extensions/gdx-bullet/jni/src/bullet/LinearMath/ |
| btVector3.h | 491 SIMD_FORCE_INLINE void setInterpolate3(const btVector3& v0, const btVector3& v1, btScalar rt)
498 __m128 r0 = _mm_mul_ps(v0.mVec128, vs);
504 float32x4_t vl = vsubq_f32(v1.mVec128, v0.mVec128);
506 mVec128 = vaddq_f32(vl, v0.mVec128);
509 m_floats[0] = s * v0.m_floats[0] + rt * v1.m_floats[0];
510 m_floats[1] = s * v0.m_floats[1] + rt * v1.m_floats[1];
511 m_floats[2] = s * v0.m_floats[2] + rt * v1.m_floats[2];
513 // m_co[3] = s * v0[3] + rt * v1[3];
648 void getSkewSymmetricMatrix(btVector3* v0,btVector3* v1,btVector3* v2) const
653 __m128 V0 = _mm_xor_ps(btvMzeroMask, V)
[all...] |
| /external/llvm/lib/Analysis/ |
| BasicAliasAnalysis.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 199 Value *V0 = I->getOperand(0);
201 if (isa<ConstantInt>(V0))
202 std::swap(V0, V1);
206 SymbolicPart = V0;
[all...] |
| /external/webp/src/dsp/ |
| yuv_sse2.c | 29 const __m128i* const V0,
44 const __m128i R0 = _mm_mulhi_epu16(*V0, k26149);
49 const __m128i G1 = _mm_mulhi_epu16(*V0, k13320);
84 const __m128i Y0 = Load_HI_16(y), U0 = Load_HI_16(u), V0 = Load_HI_16(v);
85 ConvertYUV444ToRGB(&Y0, &U0, &V0, R, G, B);
93 const __m128i Y0 = Load_HI_16(y), U0 = Load_UV_HI_8(u), V0 = Load_UV_HI_8(v);
94 ConvertYUV444ToRGB(&Y0, &U0, &V0, R, G, B);
680 __m128i r0, g0, b0, r1, g1, b1, U0, V0, U1, V1;
686 ConvertRGBToUV(&r0, &g0, &b0, &U0, &V0);
696 V0 = _mm_packus_epi16(V0, V1)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 396 Value *V0 = I->getOperand(0);
398 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) {
404 Addend0.set(C, V0);
559 Value *V0 = I->getOperand(0);
561 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) &&
[all...] |
| InstCombineCalls.cpp | 616 Value *V0 = LowInputSelect ? II.getArgOperand(1) : II.getArgOperand(0);
620 V0 = LowHalfZero ? ZeroVector : V0;
634 return Builder.CreateShuffleVector(V0, V1, ShuffleMask);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 261 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
262 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
263 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
264 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
267 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
268 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
269 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 319 static const MCPhysReg VecLstS[] = { Hexagon::V0, Hexagon::V1,
484 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
489 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | [all...] |
| LoopVectorize.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/robolectric/v1/lib/main/ |
| sqlite-jdbc-3.7.2.jar | |
