| /external/vixl/src/vixl/a64/ |
| instructions-a64.h | 137 enum AddrMode {
|
| assembler-a64.h | 720 AddrMode addrmode = Offset);
731 AddrMode addrmode = Offset);
736 AddrMode addrmode() const { return addrmode_; }
751 AddrMode addrmode_;
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | 377 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
378 : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode) {
410 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
411 : base_(base), regoffset_(NoReg), addrmode_(addrmode) {
417 VIXL_ASSERT((addrmode == Offset) || (addrmode == PostIndex));
431 VIXL_ASSERT(addrmode == Offset);
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 465 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
466 : base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode),
499 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
500 : base_(base), addrmode_(addrmode) {
508 DCHECK(addrmode == Offset);
522 DCHECK(addrmode == Offset);
[all...] |
| simulator-arm64.cc | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 157 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
169 switch (AddrMode) {
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 271 const AddrMode &AM,
|
| /external/v8/src/arm/ |
| assembler-arm.cc | 319 MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) {
334 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) {
344 ShiftOp shift_op, int shift_imm, AddrMode am) {
354 NeonMemOperand::NeonMemOperand(Register rn, AddrMode am, int align) {
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 302 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
308 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
344 const AddrMode &AM, Type *Ty,
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 512 const AddrMode &AM, Type *Ty,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
