| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_DeblockingLuma_unsafe_s.s | 65 dMask_0 DN D14.U8
|
| armVCM4P10_Interpolate_Chroma_s.s | 78 dCCoeff DN D14.U8
|
| omxVCM4P10_FilterDeblockingChroma_VerEdge_I_s.s | 101 dMask_0 DN D14.U8
|
| omxVCM4P10_FilterDeblockingLuma_HorEdge_I_s.s | 99 dMask_0 DN D14.U8
|
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.s | 145 dMask_0 DN D14.U8
|
| omxVCM4P10_PredictIntraChroma_8x8_s.s | 141 dLeft7minus0U8 DN D14.U8
|
| omxVCM4P10_PredictIntra_16x16_s.s | 148 dLeft15minus0 DN D14.S16
|
| /external/libhevc/common/arm/ |
| ihevc_sao_edge_offset_class2_chroma.s | 394 VMOV.8 D14[0],r8 @I sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[(ht_tmp - 1 - row) * 2]), sign_up, 0)
398 VMOV.8 D14[1],r4 @I sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[1] - pu1_src_left_cpy[(ht_tmp - 1 - row) * 2 + 1]), sign_up, 1)
480 VMOV.8 D14[0],r8 @II sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[(ht_tmp - 1 - row) * 2]), sign_up, 0)
496 VMOV.8 D14[1],r11 @II sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[1] - pu1_src_left_cpy[(ht_tmp - 1 - row) * 2 + 1]), sign_up, 1)
522 VMOV.8 d14[0],r4 @III sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[(ht_tmp - 1 - row) * 2]), sign_up, 0)
533 VMOV.8 D14[1],r10 @III sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[1] - pu1_src_left_cpy[(ht_tmp - 1 - row) * 2 + 1]), sign_up, 1)
617 VMOV.8 D14[0],r8 @sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[(ht_tmp - 1 - row) * 2]), sign_up, 0)
[all...] |
| ihevc_sao_edge_offset_class2.s | 290 VMOV.8 D14[0],r4 @I sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[ht_tmp - 1 - row]), sign_up, 0)
372 VMOV.8 D14[0],r4 @II sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[ht_tmp - 1 - row]), sign_up, 0)
390 VMOV.8 D14[0],r2 @III sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[ht_tmp - 1 - row]), sign_up, 0)
467 VMOV.8 D14[0],r4 @sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[ht_tmp - 1 - row]), sign_up, 0)
604 VMOV.8 d14[0],r8 @sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[0] - pu1_src_left_cpy[ht_tmp - 1 - row]), sign_up, 0)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 120 case AArch64::D14:
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 413 // D14/D15 pair = 0x00000800
423 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
|
| /external/valgrind/memcheck/ |
| mc_machine.c | [all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 321 dRow7 DN D14.U8
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 126 case AArch64::D14: return AArch64::B14;
166 case AArch64::B14: return AArch64::D14;
[all...] |
| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 479 vld1.8 {d14, d15}, [r2], r4 @ load ref3 Row 1
487 vabal.u8 q12, d14, d8
506 vld1.8 {d14, d15}, [r2], r4 @ load ref3 Row 1
512 vabal.u8 q12, d14, d8
651 vadd.i16 d6, d14, d15 @ xy top
900 @;Q7 -> D14:D15
905 vadd.u16 d14, d14, d15
910 @;D14 : sad_left
916 vpaddl.u16 d15, d14
[all...] |
| /art/compiler/utils/arm/ |
| managed_register_arm_test.cc | 162 reg = ArmManagedRegister::FromDRegister(D14);
169 EXPECT_EQ(D14, reg.AsDRegister());
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackend.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 95 SP::D14, SP::D30, SP::D15, SP::D31 };
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 125 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
[all...] |
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | [all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 526 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
[all...] |
| /external/libavc/common/arm/ |
| ih264_deblk_chroma_a9.s | 204 vrshrn.i16 d14, q7, #2
278 vtbl.8 d14, {d16}, d12 @
285 vmovl.u8 q7, d14 @
305 vadd.i8 d14, d14, d30 @Q7 = C = C0+1
309 vmov.i8 d15, d14 @
439 vmovn.u16 d14, q7
828 vrshrn.i16 d14, q7, #2
[all...] |
| ih264_iquant_itrans_recon_a9.s | 193 vadd.s16 d14, d10, d12 @x0 = q0 + q1;
368 vadd.s16 d14, d10, d12 @x0 = q0 + q1;
584 vqrshrn.s32 d14, q8, #0x6 @ D14 = c[i] = ((q[i] + 32) >> 6) where i = 56..59
604 vswp d7, d14 @ Q6/Q7 = Row order x6/x7
619 vaddl.s16 q12, d14, d2 @ y3 (0-3) 1+7
622 vsubl.s16 q10, d14, d2 @ y5 (0-3) 7-1
667 vsubw.s16 q10, q10, d14 @
675 vsubw.s16 q10, q10, d14 @
679 vqmovn.s32 d14, q12
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 287 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
