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  /external/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
42 #define DEBUG_TYPE "hexagon-lowering"
44 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
46 cl::desc("Control jump table emission on Hexagon target"));
48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
50 cl::desc("Enable Hexagon SDNode scheduling"));
100 // Implement calling convention for Hexagon.
277 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4
    [all...]
HexagonStoreWidening.cpp 24 #define DEBUG_TYPE "hexagon-widen-stores"
69 return "Hexagon Store Widening";
118 case Hexagon::S4_storeirb_io:
119 case Hexagon::S4_storeirh_io:
120 case Hexagon::S4_storeiri_io: {
141 INITIALIZE_PASS_BEGIN(HexagonStoreWidening, "hexagon-widen-stores",
144 INITIALIZE_PASS_END(HexagonStoreWidening, "hexagon-widen-stores",
145 "Hexagon Store Widening", false, false)
155 case Hexagon::S4_storeirb_io:
156 case Hexagon::S4_storeirh_io
    [all...]
HexagonEarlyIfConv.cpp 10 // This implements a Hexagon-specific if-conversion pass that runs on the
62 #define DEBUG_TYPE "hexagon-eif"
92 cl::opt<bool> EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden,
95 cl::desc("Size limit in Hexagon early if-conversion"));
143 return "Hexagon early if conversion";
203 INITIALIZE_PASS(HexagonEarlyIfConversion, "hexagon-eif",
204 "Hexagon early if conversion", false, false)
227 if (Opc != Hexagon::J2_jumpt && Opc != Hexagon::J2_jumpf)
238 assert(T2I == B->end() || T2I->getOpcode() == Hexagon::J2_jump)
    [all...]
HexagonMCInstLower.cpp 1 //===- HexagonMCInstLower.cpp - Convert Hexagon MachineInstr to an MCInst -===//
10 // This file contains code to lower Hexagon MachineInstrs to their corresponding
15 #include "Hexagon.h"
39 // Populate the relocation type based on Hexagon target flags
75 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
79 if (MI->getOpcode() == Hexagon::ENDLOOP1) {
HexagonExpandCondsets.cpp 107 return "Hexagon Expand Condsets";
192 case Hexagon::subreg_loreg:
194 case Hexagon::subreg_hireg:
196 case Hexagon::NoSubRegister:
206 case Hexagon::C2_mux:
207 case Hexagon::C2_muxii:
208 case Hexagon::C2_muxir:
209 case Hexagon::C2_muxri:
210 case Hexagon::MUX64_rr:
651 using namespace Hexagon;
    [all...]
HexagonBitTracker.cpp 15 #include "Hexagon.h"
81 using namespace Hexagon;
177 using namespace Hexagon;
892 case Hexagon::J2_jumpf:
893 case Hexagon::J2_jumpfnew:
894 case Hexagon::J2_jumpfnewpt:
896 case Hexagon::J2_jumpt:
897 case Hexagon::J2_jumptnew:
898 case Hexagon::J2_jumptnewpt:
903 case Hexagon::J2_jump
    [all...]
HexagonISelLowering.h 1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
18 #include "Hexagon.h"
169 return Hexagon::R0;
176 return Hexagon::R1;
HexagonGenInsert.cpp 31 #include "Hexagon.h"
473 return "Hexagon generate \"insert\" instructions";
598 return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;
653 if (DstRC == &Hexagon::DoubleRegsRegClass)
    [all...]
  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonAsmBackend.cpp 1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
10 #include "Hexagon.h"
26 using namespace Hexagon;
28 #define DEBUG_TYPE "hexagon-asm-backend"
61 return Hexagon::NumTargetFixupKinds;
65 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
188 HMI.getOpcode() != Hexagon::C4_addipc))
300 "Hexagon relaxInstruction only works on bundles");
HexagonFixupKinds.h 1 //===-- HexagonFixupKinds.h - Hexagon Specific Fixup Entries --------------===//
16 namespace Hexagon {
134 } // namespace Hexagon
HexagonMCTargetDesc.cpp 1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
10 // This file provides Hexagon specific target descriptions.
15 #include "Hexagon.h"
45 cl::desc("Disable looking for compound instructions for Hexagon"));
49 cl::desc("Disable looking for duplex instructions for Hexagon"));
65 InitHexagonMCRegisterInfo(X, Hexagon::R0);
125 if (Bits.to_ullong() & llvm::Hexagon::ArchV5)
156 MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
HexagonInstPrinter.cpp 1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
10 // This class prints an Hexagon MCInst to a .s file.
77 ME.setOpcode(Hexagon::ENDLOOP0);
84 ME.setOpcode(Hexagon::ENDLOOP1);
HexagonMCELFStreamer.cpp 1 //=== HexagonMCELFStreamer.cpp - Hexagon subclass of MCELFStreamer -------===//
16 #include "Hexagon.h"
43 if (MCK.getOpcode() != Hexagon::BUNDLE) {
HexagonELFObjectWriter.cpp 1 //===-- HexagonELFObjectWriter.cpp - Hexagon Target Descriptions ----------===//
10 #include "Hexagon.h"
17 #define DEBUG_TYPE "hexagon-elf-writer"
20 using namespace Hexagon;
HexagonShuffler.cpp 11 // packet formation rules of the Hexagon ISA.
15 #define DEBUG_TYPE "hexagon-shuffle"
19 #include "Hexagon.h"
301 if (HexagonMCInstrInfo::getDesc(MCII, *ID).getOpcode() != Hexagon::A2_nop)
  /external/clang/include/clang/Basic/
TargetBuiltins.h 139 /// \brief Hexagon builtins
140 namespace Hexagon {
  /external/clang/lib/Basic/
Targets.cpp     [all...]
  /external/llvm/
configure     [all...]

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