| /external/vixl/test/ |
| test-simulator-a64.cc | [all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_s.h | 250 TBH [pc, $v, LSL#1]
257 ADD pc, pc, $v, LSL #2
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_s.h | 253 TBH [pc, $v, LSL#1]
260 ADD pc, pc, $v, LSL #2
|
| /art/compiler/utils/arm/ |
| assembler_thumb2.cc | [all...] |
| assembler_arm32.cc | [all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.cc | 371 VIXL_ASSERT((shift_ == LSL) && (shift_amount_ <= 4));
406 VIXL_ASSERT(shift == LSL);
428 VIXL_ASSERT(shift_ == LSL);
[all...] |
| assembler-a64.h | 659 // where <shift> is one of {LSL, LSR, ASR, ROR}.
664 Shift shift = LSL,
677 // This returns an LSL shift (<= 4) operand as an equivalent extend operand,
723 Shift shift = LSL,
[all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | 107 return Operand(InputRegister32(index), LSL, InputInt5(index + 1));
135 return Operand(InputRegister64(index), LSL, InputInt6(index + 1));
173 LSL, InputInt32(index + 2));
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.h | 573 // where <shift> is one of {LSL, LSR, ASR, ROR}.
578 Shift shift = LSL,
604 // This returns an LSL shift (<= 4) operand as an equivalent extend operand,
640 Shift shift = LSL,
1190 void lsl(const Register& rd, const Register& rn, int shift) { function in class:v8::internal::Assembler
[all...] |
| disasm-arm64.cc | 314 if (rn_is_zr && (instr->ImmDPShift() == 0) && (instr->ShiftDP() == LSL)) {
476 mnemonic = "lsl";
601 FORMAT(LSLV, "lsl");
[all...] |
| constants-arm64.h | 331 LSL = 0x0,
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb2_bad_reg.s | 137 @ LSL (immediate)
138 lsl r13, r0, #1
139 lsl r15, r0, #1
140 lsl r0, r13, #1
141 lsl r0, r15, #1
142 @ LSL (register)
143 lsl.w r13, r0, r1
144 lsl.w r15, r0, r1
145 lsl.w r0, r13, r1
146 lsl.w r0, r15, r
[all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 184 "lsl", "lsr", "asr", "ror"
198 if ((instr->RegShiftValue() == 0) && (shift == LSL) && (shift_amount == 0)) {
[all...] |
| assembler-arm.cc | 298 // ROR #0 is functionally equivalent to LSL #0 and this allow us to encode
300 shift_op = LSL;
337 shift_op_ = LSL;
[all...] |
| /external/v8/src/ic/arm/ |
| ic-arm.cc | 543 __ ldr(scratch, MemOperand(address, key, LSL, kPointerSizeLog2, PreIndex));
[all...] |
| /external/v8/src/ic/arm64/ |
| ic-arm64.cc | 212 __ Ldr(scratch2, MemOperand(scratch1, scratch2, LSL, kPointerSizeLog2));
[all...] |
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| fastquant.cpp | 22 #define LSL 18
386 q_value = smulbb(q_scale, coeff); /*mov q_value, coeff, lsl #14 */
|
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 157 "LSL", "LSR", "ASR", "ROR"
470 if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_type == LSL)
1085 LOG_INSTR("ADD X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift);
[all...] |
| /external/v8/src/crankshaft/arm64/ |
| lithium-codegen-arm64.cc | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-tbl.h | 301 /* e.g. LSL <Wd>, <Wn>, #<uimm>. */
1165 /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */
1168 QLF2(V_2S, LSL), \
1169 QLF2(V_4S, LSL), \
1179 /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */
1182 QLF2(V_4H, LSL), \
1183 QLF2(V_8H, LSL), \
1193 /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */
1196 QLF2(V_8B, LSL), \
1197 QLF2(V_16B, LSL), \
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_sao_edge_offset_class3.s | 341 ADD r8,r0,r1,LSL #1 @II *pu1_src + src_strd
466 ADD r8,r0,r1,LSL #1 @*pu1_src + src_strd
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| illegal.l | 38 [^:]*:68: Error: .*`strb x0,\[sp,x1,lsl#0\]'
39 [^:]*:69: Error: .*`strb w7,\[x30,x0,lsl\]'
40 [^:]*:70: Error: .*`strb w7,\[x30,x0,lsl#1\]'
145 [^:]*:203: Error: .*`movz x1,#:abs_g2:u48,lsl#16'
146 [^:]*:204: Error: .*`movz x1,0xddee,lsl#8'
154 [^:]*:214: Error: .*`bic v0.4s,#1,lsl#31'
157 [^:]*:220: Error: .*`movi v0.4s,#127,lsl#4'
159 [^:]*:224: Error: .*`mvni v0.4s,#127,lsl#4'
509 [^:]*:481: Error: .*`add x0,x1,#20,LSL#16'
512 [^:]*:484: Error: .*`add x0,x1,#20,LSL'
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 270 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
317 return AArch64_AM::LSL;
337 /// is not shifted, set the Shift operand to default of "LSL 0". The logical
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 115 AsmMnemonic = "lsl";
119 AsmMnemonic = "lsl";
199 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 499 LSL,
[all...] |
