/external/v8/src/regexp/arm/ |
regexp-macro-assembler-arm.cc | 688 __ sub(r0, r0, Operand(r1, LSL, (mode_ == UC16) ? 1 : 0)); [all...] |
/external/v8/test/cctest/ |
test-assembler-arm.cc | 186 __ mov(r2, Operand(r2, LSL, 2)); 417 __ usat(r3, 1, Operand(r0, LSL, 16)); // Sat (0xFFFF<<16) to 0-1 = 0x0. [all...] |
test-assembler-ppc.cc | 429 __ usat(r3, 1, Operand(r0, LSL, 16)); // Sat (0xFFFF<<16) to 0-1 = 0x0.
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/art/compiler/optimizing/ |
code_generator_arm64.cc | 686 // calls to vixl::MacroAssembler::Lsl and 721 __ Lsl(index_reg, index_reg, Primitive::ComponentSizeShift(type)); [all...] |
/external/v8/src/arm/ |
macro-assembler-arm.h | [all...] |
simulator-arm.cc | [all...] |
/external/v8/src/arm64/ |
assembler-arm64.cc | [all...] |
simulator-arm64.cc | 953 case LSL: [all...] |
/external/vixl/src/vixl/a64/ |
macro-assembler-a64.h | [all...] |
constants-a64.h | 267 LSL = 0x0, [all...] |
disasm-a64.cc | 328 if (rn_is_zr && (instr->ImmDPShift() == 0) && (instr->ShiftDP() == LSL)) { 489 mnemonic = "lsl"; 615 FORMAT(LSLV, "lsl"); [all...] |
simulator-a64.cc | 324 case LSL: [all...] |
/external/mesa3d/src/mesa/x86/ |
assyntax.h | 526 #define LSL(a, b) CHOICE(lsl ARG2(a,b), lsl ARG2(a,b), lsl ARG2(b,a)) [all...] |
/external/llvm/test/MC/ARM/ |
v8_IT_manual.s | 132 cmpge r3, r4, lsl #1 160 @ LSL imm, encoding T1 164 @ LSL imm, encoding T2 (32-bit) 168 @ LSL reg, encoding T1 172 @ LSL reg, encoding T2 (32-bit) [all...] |
basic-thumb2-instructions.s | 49 adcs r0, r1, r3, lsl #7 58 @ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10] 120 adds r7, r3, r1, lsl #31 141 @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77] 247 ands r2, r1, r7, lsl #1 253 @ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02] 351 bic r11, r2, r6, lsl #12 360 bic r4, r2, lsl #31 370 @ CHECK: bic.w r11, r2, r6, lsl #12 @ encoding: [0x22,0xea,0x06,0x3b] 378 @ CHECK: bic.w r4, r4, r2, lsl #31 @ encoding: [0x24,0xea,0xc2,0x74 [all...] |
basic-arm-instructions.s | 70 adc r4, r5, r6, lsl #1 71 adc r4, r5, r6, lsl #31 82 adc r6, r7, r8, lsl r9 90 adc r4, r5, lsl #1 91 adc r4, r5, lsl #31 101 adc r6, r7, lsl r9 109 @ CHECK: adc r4, r5, r6, lsl #1 @ encoding: [0x86,0x40,0xa5,0xe0] 110 @ CHECK: adc r4, r5, r6, lsl #31 @ encoding: [0x86,0x4f,0xa5,0xe0] 120 @ CHECK: adc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xa7,0xe0] 127 @ CHECK: adc r4, r4, r5, lsl #1 @ encoding: [0x85,0x40,0xa4,0xe0 [all...] |
/external/v8/src/crankshaft/arm64/ |
lithium-arm64.cc | [all...] |
/external/valgrind/none/tests/arm/ |
v6intARM.stdout.exp | 37 LSL 38 lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 39 lsl r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000 40 lsl r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000 41 lsl r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000 42 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000 43 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000 44 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000 45 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000 46 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000 [all...] |
/external/v8/src/full-codegen/arm/ |
full-codegen-arm.cc | [all...] |