| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 416 unsigned Mask = (0xFFFFFFFFU >> (32-NBits));
417 unsigned Val = (SO.getImm() & Mask) << Shift;
|
| HexagonExpandCondsets.cpp | 220 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
223 Map.insert(std::make_pair(RR.Reg, Mask));
225 F->second |= Mask;
234 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
235 if (Mask & F->second)
[all...] |
| /external/mesa3d/src/gallium/state_trackers/d3d1x/d3dapi/ |
| d3d11shader.idl | 54 BYTE Mask;
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| netioapi.h | 351 ULONG Mask,
357 PULONG Mask
|
| d3d10shader.h | 93 BYTE Mask;
|
| d3d11shader.h | 131 BYTE Mask;
|
| fltdefs.h | 105 PBYTE Mask;
|
| traffic.h | 73 PVOID Mask;
|
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 208 static bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
211 bool llvm::MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
214 return ::MaskedValueIsZero(V, Mask, DL, Depth,
390 APInt Mask = APInt::getHighBitsSet(BitWidth, CommonPrefixBits);
391 KnownOne &= Range.getUnsignedMax() & Mask;
392 KnownZero &= ~Range.getUnsignedMax() & Mask;
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ValueTracking.h | 102 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
103 /// this predicate to simplify operations downstream. Mask is known to be
108 /// where V is a vector, the mask, known zero, and known one values are the
111 bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 803 uint64_t Mask = 1;
805 if (ErrorInfo & Mask) {
807 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
809 Mask <<= 1;
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_cc.c | 210 cc->cc2.depth_write_enable = ctx->Depth.Mask;
|
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nv10_state_raster.c | 101 PUSH_DATAb(push, ctx->Depth.Mask);
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMELFStreamer.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 564 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
566 if (!Mask)
569 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
572 return SDValue(); // Mask+1 is not a power of 2
660 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
661 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
686 APInt Mask, InvMask;
688 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
692 if (isVSplat(Op0Op0, Mask, IsLittleEndian))
[all...] |
| MipsISelLowering.cpp | 62 // If I is a shifted mask, set the size (Size) and the first bit of the
63 // mask (Pos), and return true.
695 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
710 // Op's second operand must be a shifted mask.
711 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
715 // Return if the shifted mask does not start at bit 0 or the sum of its size
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | 378 /// mask for the block BB.
[all...] |
| /external/llvm/include/llvm/IR/ |
| IRBuilder.h | 428 CallInst *CreateMaskedLoad(Value *Ptr, unsigned Align, Value *Mask,
433 Value *Mask);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| SROA.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 150 unsigned Mask:4; // Condition mask for instructions.
155 // 4 - trailingzeroes(mask)
159 // implied in the mask, so needs special
169 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
175 unsigned TZ = countTrailingZeros(ITState.Mask);
440 unsigned Mask:4;
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveIntervalAnalysis.cpp | 230 if (const uint32_t *Mask = MBB.getBeginClobberMask(TRI)) {
232 RegMaskBits.push_back(Mask);
245 if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
247 RegMaskBits.push_back(Mask);
250 // Compute the number of register mask instructions in this block.
747 // Compute a mask of lanes that are defined.
865 // Register mask functions
885 // We are going to enumerate all the register mask slots contained in LI.
900 // *SlotI overlaps LI. Collect mask bits.
907 // Remove usable registers clobbered by this mask
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | [all...] |
