| /external/pdfium/core/ |
| pdfiumfpdfapi.mk | 14 # Mask some warnings. These are benign, but we probably want to fix them
|
| /external/v8/src/arm64/ |
| simulator-arm64.h | 109 #define DEFINE_WRITE_IGNORE_MASK(Name, Mask) \
110 static const uint32_t Name##WriteIgnoreMask = ~static_cast<uint32_t>(Mask);
|
| /external/v8/src/ic/arm64/ |
| ic-arm64.cc | [all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | [all...] |
| Constants.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 107 ArrayRef<int> Mask) const;
219 ArrayRef<int> Mask) const {
227 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
231 int Idx = Mask[i];
654 // We generate a shuffle of InVec and ScVec, so the shuffle mask
[all...] |
| LegalizeFloatTypes.cpp | 171 // Mask = ~(1 << (Size-1))
174 SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT);
176 return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
270 SDValue Mask = DAG.getNode(
274 Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
275 LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | [all...] |
| AMDGPUISelLowering.cpp | [all...] |
| /external/clang/lib/Basic/ |
| SourceManager.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 574 /// which must be a vector type, must match the number of mask elements
575 /// NumElts. An integer mask element equal to -1 is treated as undefined.
581 "Must have the same number of vector elements as mask elements!");
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 103 "Invalid mask register as write-mask!");
196 unsigned Mask = CD8_Scale - 1;
197 assert((CD8_Scale & Mask) == 0 && "Invalid memory object size.");
198 if (Value & Mask) // Unaligned offset
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 93 // The lane mask is simply the union of all sub-indices.
97 assert(M && "Missing lane mask, sub-register cycle?");
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm.c | 513 if (ctx->Depth.Test && ctx->Depth.Mask) /* ?? */
|
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nv10_context.c | 186 if ((buffers & BUFFER_BIT_DEPTH) && ctx->Depth.Mask) {
|
| nv20_context.c | 77 if (buffers & BUFFER_BIT_DEPTH && ctx->Depth.Mask)
|
| /external/mesa3d/src/mesa/drivers/x11/ |
| xm_line.c | 469 && ctx->Depth.Mask==GL_TRUE
|
| xm_tri.c | 1032 && ctx->Depth.Mask==GL_TRUE
1059 && ctx->Depth.Mask==GL_TRUE
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| ntdef.h | 625 KAFFINITY Mask;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 160 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
162 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
576 // store is the first one. Mask all but that bit.
[all...] |
| /external/vixl/src/vixl/a64/ |
| debugger-a64.cc | 620 const uint64_t mask = 0xffffffffffffffff >> (64 - format_size); local
628 data &= mask;
642 const uint64_t mask = 0xffffffffffffffff >> (64 - format_size); local
653 data &= mask;
662 switch (instr->Mask(ExceptionMask)) {
746 VIXL_ASSERT(instr->Mask(ExceptionMask) == BRK);
[all...] |
| /external/pdfium/third_party/lcms2-2.6/src/ |
| cmspack.c | 60 cmsUInt32Number Mask;
67 cmsUInt32Number Mask;
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 62 // instructions that for the IT block. Firstcond and Mask correspond to the
64 void setITState(char Firstcond, char Mask) {
67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
4911 unsigned mask = fieldFromInstruction(Insn, 0, 4); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
