| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 258 const uint64_t Mask = 0xFFFF;
262 Imm &= ~(Mask << (Idx * 16));
265 Imm |= Mask << (Idx * 16);
289 const uint64_t Mask = 0xFFFF;
312 uint64_t Inside = Mask;
345 OrrImm = updateImm(OrrImm, Idx, Inside != Mask);
407 const unsigned Mask = 0xFFFF;
429 const unsigned Chunk = (Imm >> Shift) & Mask;
430 if (Chunk == Mask)
533 unsigned Imm16 = (Imm >> Shift) & Mask;
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 155 unsigned &SrcReg2, int &Mask, int &Value) const override;
157 unsigned SrcReg2, int Mask, int Value,
205 // When returning true, set Cond to the mask of condition-code
227 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
229 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
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| SystemZInstrInfo.cpp | 26 // Return a mask with Count low bits set.
407 int &Mask, int &Value) const {
416 Mask = ~0;
491 int Mask, int Value,
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| LowerBitSets.cpp | 118 // in the mask gives us the log2 of the alignment of all offsets, which
121 uint64_t Mask = 0;
124 Mask |= Offset;
131 if (Mask != 0)
132 BSI.AlignLog2 = countTrailingZeros(Mask, ZB_Undefined);
203 Constant *Mask;
347 // we know the offset and mask to use.
359 BAI->Mask = ConstantExpr::getPtrToInt(MaskGlobal, Int8Ty);
375 uint8_t Mask;
376 BAB.allocate(BAI->Bits, BAI->BitSize, ByteArrayOffsets[I], Mask);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 39 /// Used to encode a step in a register lane mask transformation.
40 /// Mask the bits specified in Mask, then rotate them Rol bits to the left
43 unsigned Mask;
46 return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
49 return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
271 // Bit mask of sub-classes including this, indexed by their EnumValue.
555 // Compute a lane mask for each sub-register index
[all...] |
| /external/opencv3/modules/cudafeatures2d/src/cuda/ |
| bf_radius_match.cu | 58 template <int BLOCK_SIZE, int MAX_DESC_LEN, bool SAVE_IMG_IDX, typename Dist, typename T, typename Mask>
59 __global__ void matchUnrolled(const PtrStepSz<T> query, int imgIdx, const PtrStepSz<T> train, float maxDistance, const Mask mask,
102 if (queryIdx < query.rows && trainIdx < train.rows && mask(queryIdx, trainIdx) && distVal < maxDistance)
114 template <int BLOCK_SIZE, int MAX_DESC_LEN, typename Dist, typename T, typename Mask>
115 void matchUnrolled(const PtrStepSz<T>& query, const PtrStepSz<T>& train, float maxDistance, const Mask& mask,
123 matchUnrolled<BLOCK_SIZE, MAX_DESC_LEN, false, Dist><<<grid, block, smemSize, stream>>>(query, 0, train, maxDistance, mask,
166 template <int BLOCK_SIZE, bool SAVE_IMG_IDX, typename Dist, typename T, typename Mask>
167 __global__ void match(const PtrStepSz<T> query, int imgIdx, const PtrStepSz<T> train, float maxDistance, const Mask mask
[all...] |
| /external/v8/src/arm64/ |
| simulator-arm64.cc | 78 uint32_t mask = ((1 << width) - 1) << lsb; local
79 DCHECK((mask & write_ignore_mask_) == 0);
81 value_ = (value_ & ~mask) | (bits & mask);
932 if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) {
960 unsignedT mask = (static_cast<unsignedT>(1) << amount) - 1; local
962 ((value & mask) << (sizeof(mask) * 8 - amount));
2172 T mask; local
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | 96 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
97 unsigned Mask;
107 LiveBundle() : Mask(0), FixCount(0) {}
110 bool isFixed() const { return !Mask || FixCount; }
122 unsigned Mask = 0;
126 Mask |= 1 << (LI.PhysReg - X86::FP0);
128 return Mask;
249 /// Adjust the live registers to be the set in Mask.
250 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
351 const unsigned Mask = calcLiveInMask(&MBB)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 116 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
117 /// rotate and mask opcode and mask operation.
118 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
475 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
484 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
491 // apply shift left to mask if it comes first
492 if (isShiftMask) Mask = Mask << Shift;
496 // apply shift right to mask if it comes firs
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 224 uint64_t Mask = (1ULL << Size) - 1;
226 if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
234 uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
235 Imm &= Mask;
242 Imm |= ~Mask;
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| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.cpp | 11 // generic vector mask.
20 // Vector Mask Decoding
269 /// immediate mask into a shuffle mask.
301 // It is not an error for the PSHUFB mask to not be a vector of i8 because the
374 // mask applies to each 128-bit lane. There can never be more than
393 assert(MaskTy->isVectorTy() && "Expected a vector constant mask!");
395 "Expected integer constant mask elements!");
403 "Constant mask has a different number of elements!");
414 "Constant mask has a different number of elements!")
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| rtmv2.h | 48 #define RTM_IPV4_LEN_FROM_MASK(Len,Mask) { ULONG _Temp_ = ntohl(Mask); (Len) = 0; RTM_CHECK_NTH_BIT(_Temp_,16,(Len)); RTM_CHECK_NTH_BIT(_Temp_,8,(Len)); RTM_CHECK_NTH_BIT(_Temp_,4,(Len)); while (_Temp_) { (Len) += 1; _Temp_ <<= 1; } }
53 #define RTM_IPV4_SET_ADDR_AND_MASK(NetAddress,Addr,Mask) (NetAddress)->AddressFamily = AF_INET; (*(ULONG *) ((NetAddress)->AddrBits)) = (Addr); RTM_IPV4_LEN_FROM_MASK((NetAddress)->NumBits,Mask)
54 #define RTM_IPV4_GET_ADDR_AND_MASK(Addr,Mask,NetAddress) (Addr) = (*(ULONG *) ((NetAddress)->AddrBits)); (Mask) = RTM_IPV4_MASK_FROM_LEN((NetAddress)->NumBits);
|
| /external/llvm/include/llvm/Bitcode/ |
| BitstreamReader.h | 347 static const unsigned Mask = sizeof(word_t) > 4 ? 0x3f : 0x1f;
353 // Use a mask to avoid undefined behavior.
354 CurWord >>= (NumBits & Mask);
371 // Use a mask to avoid undefined behavior.
372 CurWord >>= (BitsLeft & Mask);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 512 // Instead, we load all significant words, mask bits off, and concatenate
734 SDValue Mask = Op.getOperand(0);
738 assert(VT.isVector() && !Mask.getValueType().isVector()
754 // Generate a mask operand.
757 // What is the size of each element in the vector mask.
760 Mask = DAG.getSelect(DL, BitTy, Mask,
765 // Broadcast the mask so that the entire vector is all-one or all zero.
766 SmallVector<SDValue, 8> Ops(NumElem, Mask);
767 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops)
[all...] |
| LegalizeVectorTypes.cpp | 317 // Vector read from all ones, scalar expects a single 1 so mask.
[all...] |
| /external/llvm/lib/Fuzzer/ |
| FuzzerMutate.cpp | 52 char Mask = 1 << Bit;
55 R = X & ~Mask;
57 R = X | Mask;
|
| /art/disassembler/ |
| disassembler_arm64.cc | 76 vixl::Instr op = instr->Mask(vixl::LoadLiteralMask);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 46 bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_sm4.h | 176 unsigned char Mask;
|
| /external/mesa3d/src/gallium/state_trackers/d3d1x/d3d1xshader/src/ |
| dxbc_parse.cpp | 82 param.Mask = sig->elements[i].mask;
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen6_depthstencil.c | 88 ds->ds2.depth_write_enable = ctx->Depth.Mask;
|
| /external/llvm/lib/Transforms/Vectorize/ |
| BBVectorize.cpp | 356 std::vector<Constant*> &Mask);
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCalls.cpp | 335 // [3:0] - zero mask for each 32-bit lane
346 // If all zero mask bits are set, this was just a weird way to
358 // If the zero mask is being used with a single input or the zero mask
366 // The zero mask may override the previous insert operation.
453 // Constant Fold - shift Index'th bit to lowest position and mask off
548 APInt Mask = APInt::getLowBitsSet(64, Length).shl(Index);
549 V00 = V00 & ~Mask;
574 /// The shuffle mask for a perm2*128 selects any two halves of two 256-bit
576 /// then ignore that half of the mask and clear that half of the vector
[all...] |
| /external/libgdx/gdx/src/com/badlogic/gdx/graphics/g3d/attributes/ |
| TextureAttribute.java | 43 protected static long Mask = Diffuse | Specular | Bump | Normal | Ambient | Emissive | Reflection;
45 public final static boolean is (final long mask) {
46 return (mask & Mask) != 0;
|
| /external/llvm/include/llvm/MC/ |
| MCSymbol.h | 408 /// Modify the flags via a mask
409 void modifyFlags(uint32_t Value, uint32_t Mask) const {
411 Flags = (Flags & ~Mask) | Value;
|
