| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 683 UnaryOp Opc;
686 UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type)
687 : OpInit(IK_UnOpInit, Type), Opc(opc), LHS(lhs) {}
696 static UnOpInit *get(UnaryOp opc, Init *lhs, RecTy *Type);
711 UnaryOp getOpcode() const { return Opc; }
730 BinaryOp Opc;
733 BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) :
734 OpInit(IK_BinOpInit, Type), Opc(opc), LHS(lhs), RHS(rhs) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 237 unsigned Opc = MI->getOpcode();
238 switch (Opc) {
[all...] |
| HexagonInstrInfo.cpp | 157 int Opc = I->getOpcode();
158 if (Opc == LOOPi || Opc == LOOPr)
161 if (Opc == EndLoopOp)
772 unsigned Opc = MI->getOpcode();
776 switch (Opc) {
[all...] |
| HexagonInstrInfo.h | 355 int getCondOpcode(int Opc, bool sense) const;
362 int getDotOldOp(const int opc) const;
370 unsigned getInvertedPredicatedOpcode(const int Opc) const;
|
| HexagonISelDAGToDAG.cpp | 860 unsigned opc; local
954 unsigned opc; local
[all...] |
| HexagonVLIWPacketizer.cpp | 488 unsigned Opc = MI->getOpcode();
489 switch (Opc) {
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfo.h | 382 int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
592 virtual int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
[all...] |
| TargetFolder.h | 109 Constant *CreateBinOp(Instruction::BinaryOps Opc,
111 return Fold(ConstantExpr::get(Opc, LHS, RHS));
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstrInfo.h | 111 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
| AMDGPUISelDAGToDAG.cpp | 308 unsigned int Opc = N->getOpcode();
317 switch (Opc) {
349 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
390 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
485 bool Signed = Opc == AMDGPUISD::BFE_I32;
732 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
735 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
759 unsigned Opc
769 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 36 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
|
| Thumb1FrameLowering.cpp | 74 unsigned Opc = Old->getOpcode();
75 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
78 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
| ThumbRegisterInfo.cpp | 163 int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
166 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
167 if (Opc != ARM::tADDhirr)
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.h | 37 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc dl,
|
| MipsConstantIslandPass.cpp | 679 int Opc = I->getOpcode();
684 int UOpc = Opc;
685 switch (Opc) {
752 if (Opc == Mips::CONSTPOOL_ENTRY)
770 switch (Opc) {
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 180 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
|
| AMDGPUInstrInfo.h | 106 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
| /external/llvm/include/llvm/IR/ |
| ConstantFolder.h | 97 Constant *CreateBinOp(Instruction::BinaryOps Opc,
99 return ConstantExpr::get(Opc, LHS, RHS);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 144 unsigned Opc = PI->getOpcode();
145 if (Opc != MSP430::POP16r && !PI->isTerminator())
|
| /external/llvm/lib/AsmParser/ |
| LLParser.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 885 unsigned Opc;
887 Opc = PPC::OR
[all...] |
| PPCISelDAGToDAG.cpp | 458 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
459 return N->getOpcode() == Opc
467 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
469 return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
471 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
725 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
726 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 65 static bool isGenericOpcode(unsigned Opc) {
66 return Opc <= TargetOpcode::GENERIC_OP_END;
[all...] |
