| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 542 const SIRegisterInfo *TRI =
544 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
576 const SIRegisterInfo *TRI =
656 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
662 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
668 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
720 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
728 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
810 unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
814 unsigned PrivateSegmentWaveByteOffsetReg = TRI->getPreloadedValue
[all...] |
| SIInstrInfo.h | 92 const TargetRegisterInfo *TRI) const final;
114 const TargetRegisterInfo *TRI) const override;
120 const TargetRegisterInfo *TRI) const override;
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| AMDGPUInstrInfo.cpp | 96 const TargetRegisterInfo *TRI) const {
105 const TargetRegisterInfo *TRI) const {
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonEarlyIfConv.cpp | 119 : FP(P), TRI(T) {}
121 const TargetRegisterInfo &TRI;
128 << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI)
139 TII(0), TRI(0), MFN(0), MRI(0), MDT(0), MLI(0) {
191 const TargetRegisterInfo *TRI;
309 DEBUG(dbgs() << "Detected " << PrintFP(FP, *TRI) << "\n");
[all...] |
| HexagonExpandCondsets.cpp | 96 MachineFunctionPass(ID), HII(0), TRI(0), MRI(0),
119 const TargetRegisterInfo *TRI;
443 DEBUG(dbgs() << "adding def " << PrintReg(DefR, TRI)
559 DEBUG(dbgs() << "removing def at " << MX << " of " << PrintReg(DefR, TRI)
663 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
664 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
[all...] |
| HexagonStoreWidening.cpp | 55 const HexagonRegisterInfo *TRI;
450 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);
600 TRI = ST.getRegisterInfo();
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| BitTracker.cpp | 45 // const TargetSpecificEvaluator TSE(TRI, MRI);
331 unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub);
332 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PhysS);
813 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
820 dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
846 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
853 dbgs() << " " << PrintReg(I->first, &ME.TRI) << " cell: "
977 dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
[all...] |
| HexagonInstrInfo.h | 157 const TargetRegisterInfo *TRI) const override;
166 const TargetRegisterInfo *TRI) const override;
|
| HexagonGenInsert.cpp | 162 : RS(S), TRI(RI) {}
167 const TargetRegisterInfo *TRI;
173 OS << ' ' << PrintReg(R, P.TRI);
391 : RL(L), TRI(RI) {}
395 const TargetRegisterInfo *TRI;
404 OS << PrintReg(*I, P.TRI);
441 : IFR(R), TRI(RI) {}
444 const TargetRegisterInfo *TRI;
450 OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI)
[all...] |
| /external/llvm/lib/CodeGen/ |
| InlineSpiller.cpp | 69 const TargetRegisterInfo &TRI;
149 TRI(*mf.getSubtarget().getRegisterInfo()),
747 MRI.getRegClass(SVI.SpillReg), &TRI);
[all...] |
| PeepholeOptimizer.cpp | 125 const TargetRegisterInfo *TRI;
430 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
440 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
686 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC,
[all...] |
| SplitKit.h | 218 const TargetRegisterInfo &TRI;
|
| IfConversion.cpp | 163 const TargetRegisterInfo *TRI;
282 TRI = ST.getRegisterInfo();
[all...] |
| ShrinkWrap.cpp | 397 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
399 TRI->requiresRegisterScavenging(MF) ? new RegScavenger() : nullptr);
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| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 80 const TargetRegisterInfo *TRI;
554 LiveRegs.init(TRI);
587 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) ==
[all...] |
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveIntervalUnion.h | 101 // Print union, using TRI to translate register names
102 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
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| MachineTraceMetrics.h | 70 const TargetRegisterInfo *TRI;
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| StackMaps.h | 223 const TargetRegisterInfo *TRI) const;
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 103 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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| MSP430FrameLowering.cpp | 185 const TargetRegisterInfo *TRI) const {
211 const TargetRegisterInfo *TRI) const {
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| MSP430InstrInfo.cpp | 41 const TargetRegisterInfo *TRI) const {
68 const TargetRegisterInfo *TRI) const{
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 729 const TargetRegisterInfo *TRI) const {
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 418 const TargetRegisterInfo *TRI) const {
439 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
440 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
454 const TargetRegisterInfo *TRI) const{
467 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
468 TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 87 const MCRegisterInfo *TRI;
205 return Reg.TRI->getRegClass(RCID).contains(getReg());
302 const MCRegisterInfo *TRI,
307 Op->Reg.TRI = TRI;
523 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
530 return !subtargetHasRegister(*TRI, RegNo);
587 const MCRegisterClass RC = TRI->getRegClass(RCID);
592 return !subtargetHasRegister(*TRI, RegNo);
[all...] |
