| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86CallFrameOptimization.cpp | 496 .addReg(Reg)
|
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 543 .addReg(DstReg, 0, SubIdx);
728 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
[all...] |
| MachineRegisterInfo.cpp | 386 .addReg(LiveIns[i].first);
|
| IfConversion.cpp | [all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| MachineBasicBlock.cpp | 400 .addReg(PhysReg, RegState::Kill);
[all...] |
| ScheduleDAGInstrs.cpp | [all...] |
| SplitKit.cpp | 440 .addReg(Edit->getReg());
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 698 .addReg(DstR, RegState::Define, DstSR)
[all...] |
| HexagonGenInsert.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 778 .addReg(VRI->second);
787 .addReg(I->getReg());
[all...] |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 395 .addReg(DestReg, getDefRegState(true), SubIdx)
397 .addImm(0).addImm(Pred).addReg(PredReg)
|
| Thumb2SizeReduction.cpp | 510 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead);
522 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 520 MIB.addReg(Branch->getOperand(0).getReg());
539 MIB.addReg(Jump->getOperand(0).getReg());
|
| MipsConstantIslandPass.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 394 .addReg(T0, RegState::Implicit)
395 .addReg(T1, RegState::Implicit);
496 .addReg(T0, RegState::Implicit)
497 .addReg(T1, RegState::Implicit);
516 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
530 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
574 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
[all...] |
| AMDILCFGStructurizer.cpp | 512 MIB.addReg(OldMI->getOperand(1).getReg(), false);
524 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
534 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 599 .addReg(DestReg, RegState::Define | RegState::Dead)
|
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 291 UpdatedVRSAVE).addReg(InVRSAVE);
292 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
306 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
337 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
[all...] |
