| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 21 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/mips64/ |
| disasm-mips64.cc | [all...] |
| assembler-mips64.h | 735 void ddivu(Register rs, Register rt);
739 void ddivu(Register rd, Register rs, Register rt);
[all...] |
| macro-assembler-mips64.cc | 1090 void MacroAssembler::Ddivu(Register rs, const Operand& rt) {
1092 ddivu(rs, rt.rm());
1097 ddivu(rs, at);
1102 void MacroAssembler::Ddivu(Register res, Register rs, const Operand& rt) {
1105 ddivu(rs, rt.rm());
1108 ddivu(res, rs, rt.rm());
1115 ddivu(rs, at);
1118 ddivu(res, rs, at);
1152 ddivu(rs, rt.rm());
1158 ddivu(rs, at)
[all...] |
| assembler-mips64.cc | 1737 void Assembler::ddivu(Register rs, Register rt) { function in class:v8::internal::Assembler
1742 void Assembler::ddivu(Register rd, Register rs, Register rt) { function in class:v8::internal::Assembler
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| loongson-2e.d | 22 .*: 7f19b81f ddivu.g \$23,\$24,\$25
|
| loongson-2f.d | 22 .*: 7319b817 ddivu.g \$23,\$24,\$25
|
| micromips.s | [all...] |
| set-arch.d | 16 00000020 <[^>]*> 012a001f ddivu zero,t1,t2
|
| mips16-64.d | 621 7da: ea7f ddivu zero,v0,v1
|
| mips16.d | 620 7da: ea7f ddivu zero,v0,v1
|
| micromips-insn32.d | [all...] |
| micromips-noinsn32.d | [all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 23 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 23 ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 71 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 75 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 75 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 80 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 82 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 82 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 82 ddivu $zero,$s0,$s1
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| mips-opc.c | [all...] |
