| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 417 switch (MI.getOpcode()) {
570 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
571 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
595 switch (MI.getOpcode()) {
635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
[all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | 89 Instruction::CastOps firstOp = Instruction::CastOps(Op->getOpcode());
235 switch (CE->getOpcode()) {
546 } else if (CE->getOpcode() == Instruction::GetElementPtr &&
633 if (CE->getOpcode() == Instruction::GetElementPtr &&
768 if (TrueVal->getOpcode() == Instruction::Select)
773 if (FalseVal->getOpcode() == Instruction::Select)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 186 if (Val.getOpcode() != ISD::LOAD)
205 switch (Op.getOpcode())
240 switch (N->getOpcode()) {
571 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
588 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
611 if (Op.getOpcode() != ISD::ADD)
617 if (N0.getOpcode() == ISD::ADD) {
620 } else if (N1.getOpcode() == ISD::ADD) {
628 if (OtherOp.getOpcode() == ISD::MUL) {
638 if (AddOp.getOperand(0).getOpcode() == ISD::MUL)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | 117 // The No Signed Wrap flag can be kept if the operation "B (I.getOpcode) C",
128 Instruction::BinaryOps Opcode = I.getOpcode();
190 Instruction::BinaryOps Opcode = I.getOpcode();
206 if (Op0 && Op0->getOpcode() == Opcode) {
235 if (Op1 && Op1->getOpcode() == Opcode) {
257 if (Op0 && Op0->getOpcode() == Opcode) {
277 if (Op1 && Op1->getOpcode() == Opcode) {
299 Op0->getOpcode() == Opcode && Op1->getOpcode() == Opcode &&
435 return Op->getOpcode();
[all...] |
| InstCombineVectorOps.cpp | 46 if (I->getOpcode() == Instruction::InsertElement && isConstant &&
49 if (I->getOpcode() == Instruction::Load && I->hasOneUse())
109 BinaryOperator::Create(B0->getOpcode(), scalarPHI, Op), *B0);
196 return BinaryOperator::Create(BO->getOpcode(), newEI0, newEI1);
235 if (CI->hasOneUse() && (CI->getOpcode() != Instruction::BitCast)) {
239 return CastInst::Create(CI->getOpcode(), EE, EI.getType());
560 switch (I->getOpcode()) {
623 switch (I->getOpcode()) {
645 BinaryOperator::Create(cast<BinaryOperator>(I)->getOpcode(),
681 return CastInst::Create(cast<CastInst>(I)->getOpcode(), NewOps[0], DestTy
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 116 switch (N->getOpcode()) {
951 switch (N->getOpcode()) {
965 switch (N->getOpcode()) {
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 227 if (MI->getOpcode() != SystemZ::MVC ||
433 return (MI->getOpcode() == Opcode &&
453 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
465 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
510 unsigned Opcode = MI->getOpcode();
538 unsigned Opcode = MI->getOpcode();
682 unsigned Opcode = MI->getOpcode();
760 unsigned Opcode = MI->getOpcode();
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| SLPVectorizer.cpp | 181 unsigned Opcode = I0->getOpcode();
185 if (!I || I->getOpcode() != ((i & 1) ? AltOpcode : Opcode))
197 unsigned Opcode = I0->getOpcode();
200 if (!I || Opcode != I->getOpcode()) {
314 unsigned Opcode = UserInst->getOpcode();
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitSimplify.cpp | 405 assert(I.getOpcode() == TargetOpcode::REG_SEQUENCE);
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| BasicBlockList.java | 140 if (insn.getOpcode().getOpcode() != RegOps.MARK_LOCAL) {
|
| /dalvik/dx/src/com/android/dx/command/findusages/ |
| FindUsages.java | 84 + " (" + OpcodeInfo.getName(one.getOpcode()) + ")");
94 + " (" + OpcodeInfo.getName(one.getOpcode()) + ")");
|
| /dalvik/dx/src/com/android/dx/rop/code/ |
| BasicBlockList.java | 140 if (insn.getOpcode().getOpcode() != RegOps.MARK_LOCAL) {
|
| /external/clang/include/clang/AST/ |
| StmtVisitor.h | 46 switch (BinOp->getOpcode()) {
83 switch (UnOp->getOpcode()) {
|
| /external/clang/lib/Sema/ |
| SemaFixItUtils.cpp | 107 if (UO->getOpcode() == UO_AddrOf) {
141 if (UO->getOpcode() == UO_Deref) {
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| BasicBlockList.java | 140 if (insn.getOpcode().getOpcode() != RegOps.MARK_LOCAL) {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 40 switch (getOpcode()) {
42 if (getOpcode() < ISD::BUILTIN_OP_END)
49 return "<<Unknown Machine Node #" + utostr(getOpcode()) + ">>";
53 const char *Name = TLI.getTargetNodeName(getOpcode());
55 return "<<Unknown Target Node #" + utostr(getOpcode()) + ">>";
57 return "<<Unknown Node #" + utostr(getOpcode()) + ">>";
119 unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
576 if (Node.getOpcode() == ISD::EntryToken)
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 186 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
263 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 256 switch (MI.getOpcode()) {
326 switch(DefInstr->getOpcode()) {
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 65 switch (Inst.getOpcode()) {
86 int Opcode = InstIn.getOpcode();
158 switch (MI.getOpcode()) {
178 unsigned Opcode = TmpInst.getOpcode();
207 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
681 switch(MI.getOpcode())
812 switch (MI.getOpcode()) {
848 switch (MI.getOpcode()) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 145 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
149 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
185 if (I->getOpcode() == Mips::PseudoReturn ||
186 I->getOpcode() == Mips::PseudoReturn64 ||
187 I->getOpcode() == Mips::PseudoIndirectBranch ||
188 I->getOpcode() == Mips::PseudoIndirectBranch64) {
201 && !isLongBranchPseudo(I->getOpcode()))
649 switch (MI->getOpcode()) {
[all...] |
| MipsMCInstLower.cpp | 202 switch (MI->getOpcode()) {
230 OutMI.setOpcode(MI->getOpcode());
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCCodeEmitter.cpp | 95 switch (MI.getOpcode()) {
149 if (MI.getOpcode() == SP::TLS_CALL) {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 184 if (MI.getOpcode() == SP::STQFri) {
196 } else if (MI.getOpcode() == SP::LDQFri) {
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 42 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
59 if (MI->getOpcode() == X86::CALLpcrel32 &&
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_debug.cpp | 350 const MCInstrDesc &TID = TII->get(Inst.getOpcode());
352 const TargetInstrDesc &TID = TII->get(Inst.getOpcode());
|
