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  /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp 260 return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
274 if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
  /external/llvm/lib/Target/SystemZ/
SystemZFrameLowering.cpp 336 if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
393 (MBBI->getOpcode() == SystemZ::STD ||
394 MBBI->getOpcode() == SystemZ::STDY))
431 unsigned Opcode = MBBI->getOpcode();
518 switch (MI->getOpcode()) {
SystemZISelLowering.cpp     [all...]
  /external/llvm/tools/llvm-diff/
DifferenceEngine.cpp 250 if (L->getOpcode() != R->getOpcode()) {
399 if (L->getOpcode() != R->getOpcode())
402 switch (L->getOpcode()) {
  /external/mesa3d/src/gallium/drivers/radeon/
SIISelLowering.cpp 72 if (TII->get(MI->getOpcode()).TSFlags & SIInstrFlags::NEED_WAIT) {
77 switch (MI->getOpcode()) {
263 switch (Op.getOpcode()) {
398 switch (N->getOpcode()) {
424 && Arg0.getOpcode() == ISD::SIGN_EXTEND
  /external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp 237 unsigned Opc = MI->getOpcode();
272 unsigned RetOpc = I->getOpcode();
457 assert((MI->getOpcode() == Hexagon::ALLOCA) && "Expected alloca");
519 unsigned RetOpc = RetI ? RetI->getOpcode() : 0;
558 unsigned COpc = PrevIt->getOpcode();
583 return It->getOpcode() == Hexagon::S2_allocframe;
587 if (I->getOpcode() == Hexagon::S2_allocframe)
    [all...]
HexagonVLIWPacketizer.cpp 296 return MI->getOpcode() == Hexagon::J2_jump;
300 switch (MI->getOpcode()) {
345 if (BI->getOpcode() == Hexagon::V6_vL32b_cur_ai) {
426 int NewOpcode = HII->getDotOldOp(MI->getOpcode());
488 unsigned Opc = MI->getOpcode();
    [all...]
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]
  /external/llvm/lib/Target/X86/
X86MCInstLower.cpp 324 switch (Inst.getOpcode()) {
437 OutMI.setOpcode(MI->getOpcode());
445 switch (OutMI.getOpcode()) {
479 switch (OutMI.getOpcode()) {
504 switch (OutMI.getOpcode()) {
521 unsigned Opcode = OutMI.getOpcode();
558 switch (OutMI.getOpcode()) {
579 switch (OutMI.getOpcode()) {
716 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
717 MI.getOpcode() == X86::TLS_base_addr64
    [all...]
  /external/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 878 switch (MI->getOpcode()) {
    [all...]
R600ControlFlowFinalizer.cpp 226 switch (MI->getOpcode()) {
395 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
508 if (MI->getOpcode() != AMDGPU::ENDIF)
510 if (MI->getOpcode() == AMDGPU::CF_ALU)
514 CFStack.requiresWorkAroundForInst(MI->getOpcode());
515 switch (MI->getOpcode()) {
639 if (TII->isExport(MI->getOpcode())) {
AMDGPUPromoteAlloca.cpp 138 switch (Inst->getOpcode()) {
207 switch (Inst->getOpcode()) {
259 if (UseInst && UseInst->getOpcode() == Instruction::PtrToInt)
  /external/llvm/lib/Analysis/
ConstantFolding.cpp 250 if (CE->getOpcode() == Instruction::PtrToInt ||
251 CE->getOpcode() == Instruction::BitCast)
390 if (CE->getOpcode() == Instruction::IntToPtr &&
543 if (CE->getOpcode() == Instruction::GetElementPtr) {
553 if (CE->getOpcode() == Instruction::BitCast)
752 if (CE && CE->getOpcode() == Instruction::Sub &&
796 if (CE->getOpcode() == Instruction::IntToPtr) {
    [all...]
  /external/llvm/lib/Target/ARM/
ARMConstantIslandPass.cpp 604 switch (MI->getOpcode()) {
687 switch (CPEMI->getOpcode()) {
718 if (I->isBranch() && I->getOpcode() == ARM::t2BR_JT)
760 unsigned Opc = I->getOpcode();
    [all...]
ARMAsmPrinter.cpp     [all...]
  /dalvik/dx/src/com/android/dx/ssa/back/
FirstFitLocalCombiningAllocator.java 270 Rop opcode = defInsn.getOpcode();
273 if (opcode != null && opcode.getOpcode() == RegOps.MOVE_PARAM) {
555 if (checkCastInsn.getOpcode().getOpcode() != RegOps.CHECK_CAST) {
747 if (insn.getOpcode().getOpcode() ==
751 insn.getOriginalRopInsn().getOpcode(),
    [all...]
  /external/dexmaker/src/dx/java/com/android/dx/ssa/back/
FirstFitLocalCombiningAllocator.java 222 Rop opcode = defInsn.getOpcode();
225 if (opcode != null && opcode.getOpcode() == RegOps.MOVE_PARAM) {
476 if (checkCastInsn.getOpcode().getOpcode() != RegOps.CHECK_CAST) {
668 if (insn.getOpcode().getOpcode() ==
672 insn.getOriginalRopInsn().getOpcode(),
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 113 if (User->getOpcode() == ISD::CopyToReg &&
196 if (User->getOpcode() == ISD::CopyToReg &&
245 if (User->getOpcode() == ISD::CopyToReg &&
352 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
477 if (User->getOpcode() == ISD::CopyToReg &&
    [all...]
  /external/clang/lib/StaticAnalyzer/Checkers/
DeadStoresChecker.cpp 109 if (BO->getOpcode() == BO_Assign) {
113 if (BO->getOpcode() == BO_Comma) {
412 if (U->getOpcode() != UO_AddrOf)
  /external/llvm/lib/Target/MSP430/
MSP430ISelDAGToDAG.cpp 183 switch (N.getOpcode()) {
354 if (N1.getOpcode() == ISD::LOAD &&
398 switch (Node->getOpcode()) {
  /external/llvm/lib/Target/NVPTX/
NVPTXGenericToNVVM.cpp 311 unsigned Opcode = C->getOpcode();
356 return Builder.CreateBinOp(Instruction::BinaryOps(C->getOpcode()),
361 return Builder.CreateCast(Instruction::CastOps(C->getOpcode()),
  /external/llvm/lib/Transforms/InstCombine/
InstCombineAddSub.cpp 358 unsigned Opcode = I->getOpcode();
395 if (I->getOpcode() == Instruction::FMul) {
442 assert((I->getOpcode() == Instruction::FAdd ||
443 I->getOpcode() == Instruction::FSub) && "Expect add/sub");
448 if (!I0 || !I1 || I0->getOpcode() != I1->getOpcode())
452 if (I0->getOpcode() == Instruction::FMul)
454 else if (I0->getOpcode() != Instruction::FDiv)
495 Value *NewAddSub = (I->getOpcode() == Instruction::FAdd) ?
525 assert((I->getOpcode() == Instruction::FAdd |
    [all...]
InstCombineCompares.cpp     [all...]
  /external/llvm/lib/Transforms/Scalar/
IndVarSimplify.cpp 294 if (Incr == nullptr || Incr->getOpcode() != Instruction::FAdd) return;
632 unsigned Opc = UseInstr->getOpcode();
645 unsigned PhiOpc = cast<Instruction>(*PB)->getOpcode();
789 bool IsSigned = Cast->getOpcode() == Instruction::SExt;
790 if (!IsSigned && Cast->getOpcode() != Instruction::ZExt)
    [all...]
  /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/
Analyzer.java 180 int insnOpcode = insnNode.getOpcode();
315 if (node.getOpcode() == JSR) {
348 switch (node.getOpcode()) {

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