| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 112 const MachineOperand &Src = MI->getOperand(1);
113 const MachineOperand &Dest = MI->getOperand(0);
138 if (!MI->getOperand(2).isImm()) {
146 if (MI->getOperand(1).getReg() != MI->getOperand(2).getReg()) {
184 MachineOperand &opnd = MI->getOperand(i);
245 unsigned SrcReg = LEA->getOperand(1 + X86::AddrBaseReg).getReg();
246 unsigned DstReg = LEA->getOperand(0).getReg();
249 LEA->getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
250 LEA->getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 63 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
85 MachineOperand &DstOp = MI.getOperand(DstIdx);
94 Mov->getOperand(MovPredSelIdx).setReg(
95 MI.getOperand(LDSPredSelIdx).getReg());
102 uint64_t Flags = MI.getOperand(3).getImm();
106 MI.getOperand(2).getImm(), // opcode
107 MI.getOperand(0).getReg(), // dst
108 MI.getOperand(1).getReg(), // src0
123 MI.getOperand(2).getImm());
129 DstReg = MI.getOperand(Chan).getReg()
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 597 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
601 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
615 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
619 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
625 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
635 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
656 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
659 GetNegatedExpression(Op.getOperand(0), DAG,
661 Op.getOperand(1), Flags);
664 GetNegatedExpression(Op.getOperand(1), DAG
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 47 isa<ConstantInt>(I->getOperand(2)))
53 (cheapToScalarize(BO->getOperand(0), isConstant) ||
54 cheapToScalarize(BO->getOperand(1), isConstant)))
58 (cheapToScalarize(CI->getOperand(0), isConstant) ||
59 cheapToScalarize(CI->getOperand(1), isConstant)))
103 unsigned opId = (B0->getOperand(0) == PN) ? 1 : 0;
105 ExtractElementInst::Create(B0->getOperand(opId), Elt,
106 B0->getOperand(opId)->getName() + ".Elt"),
138 if (Constant *C = dyn_cast<Constant>(EI.getOperand(0)))
144 if (ConstantInt *IdxC = dyn_cast<ConstantInt>(EI.getOperand(1)))
[all...] |
| InstCombineShifts.cpp | 25 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType());
26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
94 if (MaskedValueIsZero(I->getOperand(0),
97 return CanEvaluateTruncated(I->getOperand(0), Ty);
114 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC, I) &&
115 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC, I);
119 CI = dyn_cast<ConstantInt>(I->getOperand(1));
134 if (IC.MaskedValueIsZero(I->getOperand(0)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 61 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
62 MachineOperand &LowRegOp = MI->getOperand(0);
68 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
69 MachineOperand &LowOffsetOp = MI->getOperand(2);
74 EarlierMI->getOperand(1).setIsKill(false);
75 EarlierMI->getOperand(3).setIsKill(false);
91 MachineOperand &OffsetMO = MI->getOperand(2);
111 unsigned Reg = MI->getOperand(0).getReg();
115 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()))
[all...] |
| SystemZElimCompare.cpp | 103 MI->getOperand(0).isReg() &&
104 MI->getOperand(0).isDef() &&
105 MI->getOperand(0).getReg() == Reg)
121 if (MI->getOperand(1).getReg() == Reg)
132 const MachineOperand &MO = MI->getOperand(I);
155 MI->getOperand(0).isDead());
163 reg = Compare->getOperand(0).getReg();
165 reg = Compare->getOperand(1).getReg();
186 if (MI->getOperand(2).getImm() != -1)
194 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP |
[all...] |
| SystemZRegisterInfo.cpp | 71 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
74 MI->getOperand(FIOperandNum + 1).getImm());
78 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
79 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
88 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
106 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
110 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
111 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
128 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
133 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 88 const MachineOperand &MO = MI->getOperand(OpNo);
149 if (!MI->getOperand(OpNo).isReg() ||
151 !MI->getOperand(OpNo+1).isReg())
158 if (MI->getOperand(OpNo).isImm())
175 const MachineOperand &Base = MI->getOperand(OpNo);
176 const MachineOperand &Offset = MI->getOperand(OpNo+1);
229 const MachineOperand &MO = MI.getOperand(1);
271 const MCOperand &Imm = MappedInst.getOperand(1);
278 MCOperand &Reg = MappedInst.getOperand(0);
292 MCOperand &Imm = MappedInst.getOperand(1)
[all...] |
| HexagonInstrInfo.cpp | 182 const MachineOperand &MO = MI->getOperand(i);
242 if (MI->getOperand(2).isFI() &&
243 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
244 FrameIndex = MI->getOperand(2).getIndex();
245 return MI->getOperand(0).getReg();
266 if (MI->getOperand(2).isFI() &&
267 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
268 FrameIndex = MI->getOperand(0).getIndex()
[all...] |
| HexagonExpandPredSpillCode.cpp | 101 MachineOperand &Op0 = MI->getOperand(0);
102 MachineOperand &Op1 = MI->getOperand(1);
103 MachineOperand &Op2 = MI->getOperand(2);
104 MachineOperand &Op3 = MI->getOperand(3); // Modifier value.
105 MachineOperand &Op4 = MI->getOperand(4);
144 MachineOperand &Op0 = MI->getOperand(0);
145 MachineOperand &Op1 = MI->getOperand(1);
146 MachineOperand &Op2 = MI->getOperand(2);
147 MachineOperand &Op4 = MI->getOperand(4); // Modifier value.
148 MachineOperand &Op5 = MI->getOperand(5)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 104 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
122 Op.getOperand(2), Op.getOperand(3));
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
125 Op.getOperand(2));
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1)
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
|
| MCInstrDesc.cpp | 47 if (MI.getOperand(i).isReg() &&
48 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
66 if (MI.getOperand(i).isReg() &&
67 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.cpp | 97 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
101 MI.getOperand(FIOperandNum + 1).getImm();
104 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
105 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
| NVPTXReplaceImageHandles.cpp | 86 MachineOperand &TexHandle = MI.getOperand(4);
90 MachineOperand &SampHandle = MI.getOperand(5);
100 MachineOperand &SurfHandle = MI.getOperand(VecSize);
107 MachineOperand &SurfHandle = MI.getOperand(0);
114 MachineOperand &Handle = MI.getOperand(1);
153 assert(TexHandleDef.getOperand(6).isSymbol() && "Load is not a symbol!");
154 StringRef Sym = TexHandleDef.getOperand(6).getSymbolName();
169 assert(TexHandleDef.getOperand(1).isGlobal() && "Load is not a global!");
170 const GlobalValue *GV = TexHandleDef.getOperand(1).getGlobal();
178 bool Res = findIndexForHandle(TexHandleDef.getOperand(1), MF, Idx)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
400 SDValue MultHi = ADDENode->getOperand(0);
401 SDValue MultLo = ADDCNode->getOperand(0);
432 ADDCNode->getOperand(1),
433 ADDENode->getOperand(1));
439 MultNode->getOperand(0),// Factor 0
440 MultNode->getOperand(1),// Factor 1
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
472 SDValue MultHi = SUBENode->getOperand(1);
473 SDValue MultLo = SUBCNode->getOperand(1)
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 73 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
78 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
81 Base = Addr.getOperand(0);
101 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
106 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
134 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
140 SDValue Chain = Node->getOperand(0);
141 SDValue N1 = Node->getOperand(1);
142 SDValue Skb = Node->getOperand(2);
143 SDValue N3 = Node->getOperand(3)
[all...] |
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 62 if (!MI->getOperand(0).isReg())
64 switch (MI->getOperand(0).getReg()) {
67 if (MI->getOperand(2).isImm() &&
68 MI->getOperand(2).getImm() == 8) {
69 switch(MI->getOperand(1).getReg()) {
86 || (!MI->getOperand(0).isReg())
87 || (MI->getOperand(0).getReg() != SP::FCC0))
110 const MCOperand &MO = MI->getOperand (opNum);
137 const MCOperand &MO = MI->getOperand(opNum+1);
152 int CC = (int)MI->getOperand(opNum).getImm()
[all...] |
| /external/llvm/lib/ExecutionEngine/Orc/ |
| ExecutionUtils.cpp | 47 ConstantStruct *CS = dyn_cast<ConstantStruct>(InitList->getOperand(I));
50 Constant *FuncC = CS->getOperand(1);
60 FuncC = dyn_cast_or_null<ConstantExpr>(CE->getOperand(0));
69 ConstantInt *Priority = dyn_cast<ConstantInt>(CS->getOperand(0));
70 Value *Data = CS->getOperand(2);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 142 return MI->getOperand(1).getReg();
145 if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) {
147 return MI->getOperand(1).getReg();
152 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
155 return MI->getOperand(1).getReg();
156 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg()
[all...] |
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 37 const MCOperand &Op = MI->getOperand(OpNo);
49 const MCOperand &Op = MI->getOperand(OpNo);
64 const MCOperand &Base = MI->getOperand(OpNo);
65 const MCOperand &Disp = MI->getOperand(OpNo+1);
92 unsigned CC = MI->getOperand(OpNo).getImm();
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyStoreResults.cpp | 93 unsigned ToReg = MI.getOperand(0).getReg();
94 unsigned FromReg = MI.getOperand(3).getReg();
103 Where->getOperand(&O - &Where->getOperand(0) + 1).getMBB();
118 assert(!MI.getOperand(0).isDead() && "Dead flag set on store result");
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 460 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
487 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
520 SDValue Op0 = N->getOperand(0);
521 SDValue Op1 = N->getOperand(1);
541 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
542 Op0.getOperand(0).getOpcode() == ISD::SRL) {
543 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
544 Op1.getOperand(0).getOpcode() != ISD::SRL) {
551 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
552 Op1.getOperand(0).getOpcode() != ISD::SRL)
[all...] |
