/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | 144 !hasTrivialKill(Cast->getOperand(0))) 156 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0))) 404 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0))) 406 unsigned Op1 = getRegForValue(I->getOperand(1)); 409 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 422 unsigned Op0 = getRegForValue(I->getOperand(0)); 425 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 428 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 456 if (const auto *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 466 unsigned Op1 = getRegForValue(I->getOperand(1)) [all...] |
SelectionDAG.cpp | 102 N = N->getOperand(0).getNode(); 109 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) 123 SDValue NotZero = N->getOperand(i); 138 if (N->getOperand(i) != NotZero && 139 N->getOperand(i).getOpcode() != ISD::UNDEF) 150 N = N->getOperand(0).getNode(); 710 assert(N->getOperand(0).getValueType() == N->getOperand(1).getValueType() && 712 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && 714 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() & [all...] |
SelectionDAGPrinter.cpp | 71 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); 100 SDValue Op = EI.getNode()->getOperand(EI.getOperand());
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/external/llvm/lib/Bitcode/Writer/ |
BitcodeWriter.cpp | 846 Metadata *MD = N->getOperand(i); [all...] |
/external/llvm/lib/Transforms/Scalar/ |
IndVarSimplify.cpp | 298 ConstantFP *IncValueVal = dyn_cast<ConstantFP>(Incr->getOperand(1)); 300 if (IncValueVal == nullptr || Incr->getOperand(0) != PN || 336 ConstantFP *ExitValueVal = dyn_cast<ConstantFP>(Compare->getOperand(1)); 807 Cast->getOperand(0)->getType())) { [all...] |
/external/apache-xml/src/main/java/org/apache/xpath/operations/ |
UnaryOperation.java | 115 public Expression getOperand(){
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/external/llvm/lib/CodeGen/ |
TargetSchedule.cpp | 130 const MachineOperand &MO = MI->getOperand(i); 146 const MachineOperand &MO = MI->getOperand(i); 211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() 282 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
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LiveDebugValues.cpp | 137 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0; 154 return MI1.getOperand(1).getImm() == MI2.getOperand(1).getImm(); 328 DMI->isIndirectDebugValue(), DMI->getOperand(0).getReg(), 0, 331 MI->getOperand(1).setImm(DMI->getOperand(1).getImm());
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LocalStackSlotAllocation.cpp | 309 if (MI->getOperand(i).isFI()) { 311 if (!MFI->isObjectPreAllocated(MI->getOperand(i).getIndex())) 313 int Idx = MI->getOperand(i).getIndex(); 347 if (!MI->getOperand(idx).isFI()) 350 if (FrameIdx == I->getOperand(idx).getIndex())
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/external/llvm/lib/IR/ |
IntrinsicInst.cpp | 37 return CE->getOperand(0);
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/external/llvm/lib/Target/AMDGPU/ |
SIFixControlFlowLiveIntervals.cpp | 79 unsigned Reg = MI.getOperand(0).getReg();
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/external/llvm/lib/Target/BPF/ |
BPFAsmPrinter.cpp | 51 const MachineOperand &MO = MI->getOperand(OpNum);
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BPFISelLowering.cpp | 479 SDValue Chain = Op.getOperand(0); 480 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 481 SDValue LHS = Op.getOperand(2); 482 SDValue RHS = Op.getOperand(3); 483 SDValue Dest = Op.getOperand(4); 493 SDValue LHS = Op.getOperand(0); 494 SDValue RHS = Op.getOperand(1); 495 SDValue TrueV = Op.getOperand(2); 496 SDValue FalseV = Op.getOperand(3); 497 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get() [all...] |
BPFMCInstLower.cpp | 48 const MachineOperand &MO = MI->getOperand(i);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsELFStreamer.cpp | 26 const MCOperand &Op = Inst.getOperand(OpIndex);
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/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | 718 return X86SelectAddress(U->getOperand(0), AM); 722 if (TLI.getValueType(DL, U->getOperand(0)->getType()) == 724 return X86SelectAddress(U->getOperand(0), AM); 730 return X86SelectAddress(U->getOperand(0), AM); 748 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 753 return X86SelectAddress(U->getOperand(0), AM); 790 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 793 Op = cast<AddOperator>(Op)->getOperand(0); 821 dyn_cast<GetElementPtrInst>(U->getOperand(0))) { 826 } else if (X86SelectAddress(U->getOperand(0), AM)) [all...] |
X86FloatingPoint.cpp | 270 unsigned DstReg = MI->getOperand(0).getReg(); 271 unsigned SrcReg = MI->getOperand(1).getReg(); 381 X86::RFP80RegClass.contains(MI->getOperand(0).getReg())) 401 const MachineOperand &MO = MI->getOperand(i); [all...] |
/external/llvm/lib/Target/XCore/InstPrinter/ |
XCoreInstPrinter.cpp | 75 const MCOperand &Op = MI->getOperand(OpNo);
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/external/llvm/lib/Transforms/Utils/ |
BypassSlowDivision.cpp | 86 Value *Dividend = Instr->getOperand(0); 87 Value *Divisor = Instr->getOperand(1); 194 DivOpInfo Key(UseSignedOp, Instr->getOperand(0), Instr->getOperand(1));
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GlobalStatus.cpp | 84 if (SI->getOperand(0) == V) 98 dyn_cast<GlobalVariable>(SI->getOperand(1))) { 99 Value *StoredVal = SI->getOperand(0); 112 cast<LoadInst>(StoredVal)->getOperand(0) == GV) {
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/external/llvm/tools/opt/ |
BreakpointPrinter.cpp | 56 auto *SP = cast_or_null<DISubprogram>(NMD->getOperand(i));
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUMCInstLower.cpp | 34 const MachineOperand &MO = MI->getOperand(i);
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/external/llvm/lib/Linker/ |
IRMover.cpp | [all...] |
/external/llvm/include/llvm/IR/ |
Operator.h | 389 return getOperand(0); 392 return getOperand(0); 460 return getOperand(0); 463 return getOperand(0); 487 return getOperand(0)->getType();
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/external/llvm/lib/Target/Hexagon/ |
HexagonBitSimplify.cpp | 406 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); 409 SL = I.getOperand(1); 410 SH = I.getOperand(3); 414 SH = I.getOperand(1); 415 SL = I.getOperand(3); 934 assert(!UseI->getOperand(0).getSubReg()); 935 unsigned DR = UseI->getOperand(0).getReg(); [all...] |