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    Searched refs:getRegisterInfo (Results 101 - 125 of 260) sorted by null

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  /external/llvm/lib/Target/SystemZ/
SystemZInstrInfo.h 199 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
SystemZShortenInst.cpp 269 TRI = ST.getRegisterInfo();
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyFrameLowering.cpp 48 MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
  /external/llvm/lib/Target/X86/
X86ExpandPseudo.cpp 186 TRI = STI->getRegisterInfo();
X86OptimizeLEAs.cpp 308 TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
  /external/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp 188 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
268 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
300 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
356 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
382 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
397 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
    [all...]
ARMFrameLowering.cpp 59 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
298 const MCRegisterInfo *MRI = Context.getRegisterInfo();
299 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
701 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
818 MF.getSubtarget().getRegisterInfo());
    [all...]
ARMBaseInstrInfo.cpp 799 const TargetRegisterInfo *TRI = &getRegisterInfo();
901 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
918 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
    [all...]
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmInstrumentation.cpp 539 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
576 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
797 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
836 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
    [all...]
  /external/llvm/lib/CodeGen/
EarlyIfConversion.cpp 157 TRI = MF.getSubtarget().getRegisterInfo();
794 TRI = STI.getRegisterInfo();
GCRootLowering.cpp 343 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
MachineCopyPropagation.cpp 338 TRI = MF.getSubtarget().getRegisterInfo();
MachineInstrBundle.cpp 120 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
ShrinkWrap.cpp 397 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
TargetInstrInfo.cpp 351 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
554 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
671 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64ConditionalCompares.cpp 195 TRI = MF.getSubtarget().getRegisterInfo();
895 TRI = MF.getSubtarget().getRegisterInfo();
  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCodeEmitter.cpp 117 MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg());
726 return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
  /external/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 309 const MCRegisterInfo *MRI = DC->getRegisterInfo();
  /external/llvm/lib/Target/AMDGPU/
AMDGPUInstrInfo.cpp 36 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
SIFoldOperands.cpp 307 const SIRegisterInfo &TRI = TII->getRegisterInfo();
  /external/llvm/lib/Target/Hexagon/
HexagonGenMux.cpp 309 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
HexagonInstrInfo.h 257 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
  /external/llvm/lib/Target/SystemZ/MCTargetDesc/
SystemZMCCodeEmitter.cpp 141 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
  /external/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 756 const auto *TRI = MF.getSubtarget().getRegisterInfo();
    [all...]
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMELFStreamer.cpp     [all...]

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