1 %default {} 2 /* 3 * Specialized 32-bit binary operation 4 * 5 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 6 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 7 * ARMv7 CPUs that have hardware division support). 8 * 9 * div-int/2addr 10 * 11 */ 12 mov r3, rINST, lsr #12 @ r3<- B 13 ubfx r9, rINST, #8, #4 @ r9<- A 14 GET_VREG r1, r3 @ r1<- vB 15 GET_VREG r0, r9 @ r0<- vA 16 cmp r1, #0 @ is second operand zero? 17 beq common_errDivideByZero 18 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 19 20 #ifdef __ARM_ARCH_EXT_IDIV__ 21 sdiv r0, r0, r1 @ r0<- op 22 #else 23 bl __aeabi_idiv @ r0<- op, r0-r3 changed 24 #endif 25 GET_INST_OPCODE ip @ extract opcode from rINST 26 SET_VREG r0, r9 @ vAA<- r0 27 GOTO_OPCODE ip @ jump to next instruction 28 /* 10-13 instructions */ 29 30
