1 %default {} 2 /* 3 * Specialized 32-bit binary operation 4 * 5 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 6 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 7 * ARMv7 CPUs that have hardware division support). 8 * 9 * div-int/lit8 10 * 11 */ 12 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC 13 mov r9, rINST, lsr #8 @ r9<- AA 14 and r2, r3, #255 @ r2<- BB 15 GET_VREG r0, r2 @ r0<- vBB 16 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 17 @cmp r1, #0 @ is second operand zero? 18 beq common_errDivideByZero 19 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 20 21 #ifdef __ARM_ARCH_EXT_IDIV__ 22 sdiv r0, r0, r1 @ r0<- op 23 #else 24 bl __aeabi_idiv @ r0<- op, r0-r3 changed 25 #endif 26 GET_INST_OPCODE ip @ extract opcode from rINST 27 SET_VREG r0, r9 @ vAA<- r0 28 GOTO_OPCODE ip @ jump to next instruction 29 /* 10-12 instructions */ 30
