1 %default {} 2 /* 3 * Specialized 32-bit binary operation 4 * 5 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 6 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 7 * ARMv7 CPUs that have hardware division support). 8 * 9 * NOTE: idivmod returns quotient in r0 and remainder in r1 10 * 11 * rem-int/lit16 12 * 13 */ 14 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 15 mov r2, rINST, lsr #12 @ r2<- B 16 ubfx r9, rINST, #8, #4 @ r9<- A 17 GET_VREG r0, r2 @ r0<- vB 18 cmp r1, #0 @ is second operand zero? 19 beq common_errDivideByZero 20 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 21 22 #ifdef __ARM_ARCH_EXT_IDIV__ 23 sdiv r2, r0, r1 24 mls r1, r1, r2, r0 @ r1<- op 25 #else 26 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 27 #endif 28 GET_INST_OPCODE ip @ extract opcode from rINST 29 SET_VREG r1, r9 @ vAA<- r1 30 GOTO_OPCODE ip @ jump to next instruction 31 /* 10-13 instructions */ 32
