1 %default {} 2 /* 3 * Specialized 32-bit binary operation 4 * 5 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 6 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 7 * ARMv7 CPUs that have hardware division support). 8 * 9 * NOTE: idivmod returns quotient in r0 and remainder in r1 10 * 11 * rem-int/lit8 12 * 13 */ 14 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 15 mov r9, rINST, lsr #8 @ r9<- AA 16 and r2, r3, #255 @ r2<- BB 17 GET_VREG r0, r2 @ r0<- vBB 18 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 19 @cmp r1, #0 @ is second operand zero? 20 beq common_errDivideByZero 21 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 22 23 #ifdef __ARM_ARCH_EXT_IDIV__ 24 sdiv r2, r0, r1 25 mls r1, r1, r2, r0 @ r1<- op 26 #else 27 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 28 #endif 29 GET_INST_OPCODE ip @ extract opcode from rINST 30 SET_VREG r1, r9 @ vAA<- r1 31 GOTO_OPCODE ip @ jump to next instruction 32 /* 10-12 instructions */ 33
