1 /**************************************************************************//** 2 * @file core_cm4.h 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 4 * @version V4.00 5 * @date 22. August 2014 6 * 7 * @note 8 * 9 ******************************************************************************/ 10 /* Copyright (c) 2009 - 2014 ARM LIMITED 11 12 All rights reserved. 13 Redistribution and use in source and binary forms, with or without 14 modification, are permitted provided that the following conditions are met: 15 - Redistributions of source code must retain the above copyright 16 notice, this list of conditions and the following disclaimer. 17 - Redistributions in binary form must reproduce the above copyright 18 notice, this list of conditions and the following disclaimer in the 19 documentation and/or other materials provided with the distribution. 20 - Neither the name of ARM nor the names of its contributors may be used 21 to endorse or promote products derived from this software without 22 specific prior written permission. 23 * 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 POSSIBILITY OF SUCH DAMAGE. 35 ---------------------------------------------------------------------------*/ 36 37 38 #if defined ( __ICCARM__ ) 39 #pragma system_include /* treat file as system include file for MISRA check */ 40 #endif 41 42 #ifndef __CORE_CM4_H_GENERIC 43 #define __CORE_CM4_H_GENERIC 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 50 CMSIS violates the following MISRA-C:2004 rules: 51 52 \li Required Rule 8.5, object/function definition in header file.<br> 53 Function definitions in header files are used to allow 'inlining'. 54 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 56 Unions are used for effective representation of core registers. 57 58 \li Advisory Rule 19.7, Function-like macro defined.<br> 59 Function-like macros are used to allow more efficient code. 60 */ 61 62 63 /******************************************************************************* 64 * CMSIS definitions 65 ******************************************************************************/ 66 /** \ingroup Cortex_M4 67 @{ 68 */ 69 70 /* CMSIS CM4 definitions */ 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 75 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */ 77 78 79 #if defined ( __CC_ARM ) 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 82 #define __STATIC_INLINE static __inline 83 84 #elif defined ( __GNUC__ ) 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 87 #define __STATIC_INLINE static inline 88 89 #elif defined ( __ICCARM__ ) 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 92 #define __STATIC_INLINE static inline 93 94 #elif defined ( __TMS470__ ) 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 96 #define __STATIC_INLINE static inline 97 98 #elif defined ( __TASKING__ ) 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 101 #define __STATIC_INLINE static inline 102 103 #elif defined ( __CSMC__ ) 104 #define __packed 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 107 #define __STATIC_INLINE static inline 108 109 #endif 110 111 /** __FPU_USED indicates whether an FPU is used or not. 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 113 */ 114 #if defined ( __CC_ARM ) 115 #if defined __TARGET_FPU_VFP 116 #if (__FPU_PRESENT == 1) 117 #define __FPU_USED 1 118 #else 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 120 #define __FPU_USED 0 121 #endif 122 #else 123 #define __FPU_USED 0 124 #endif 125 126 #elif defined ( __GNUC__ ) 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 128 #if (__FPU_PRESENT == 1) 129 #define __FPU_USED 1 130 #else 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 132 #define __FPU_USED 0 133 #endif 134 #else 135 #define __FPU_USED 0 136 #endif 137 138 #elif defined ( __ICCARM__ ) 139 #if defined __ARMVFP__ 140 #if (__FPU_PRESENT == 1) 141 #define __FPU_USED 1 142 #else 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 144 #define __FPU_USED 0 145 #endif 146 #else 147 #define __FPU_USED 0 148 #endif 149 150 #elif defined ( __TMS470__ ) 151 #if defined __TI_VFP_SUPPORT__ 152 #if (__FPU_PRESENT == 1) 153 #define __FPU_USED 1 154 #else 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 156 #define __FPU_USED 0 157 #endif 158 #else 159 #define __FPU_USED 0 160 #endif 161 162 #elif defined ( __TASKING__ ) 163 #if defined __FPU_VFP__ 164 #if (__FPU_PRESENT == 1) 165 #define __FPU_USED 1 166 #else 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 168 #define __FPU_USED 0 169 #endif 170 #else 171 #define __FPU_USED 0 172 #endif 173 174 #elif defined ( __CSMC__ ) /* Cosmic */ 175 #if ( __CSMC__ & 0x400) // FPU present for parser 176 #if (__FPU_PRESENT == 1) 177 #define __FPU_USED 1 178 #else 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 180 #define __FPU_USED 0 181 #endif 182 #else 183 #define __FPU_USED 0 184 #endif 185 #endif 186 187 #include <stdint.h> /* standard types definitions */ 188 #include <core_cmInstr.h> /* Core Instruction Access */ 189 #include <core_cmFunc.h> /* Core Function Access */ 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ 191 192 #ifdef __cplusplus 193 } 194 #endif 195 196 #endif /* __CORE_CM4_H_GENERIC */ 197 198 #ifndef __CMSIS_GENERIC 199 200 #ifndef __CORE_CM4_H_DEPENDANT 201 #define __CORE_CM4_H_DEPENDANT 202 203 #ifdef __cplusplus 204 extern "C" { 205 #endif 206 207 /* check device defines and use defaults */ 208 #if defined __CHECK_DEVICE_DEFINES 209 #ifndef __CM4_REV 210 #define __CM4_REV 0x0000 211 #warning "__CM4_REV not defined in device header file; using default!" 212 #endif 213 214 #ifndef __FPU_PRESENT 215 #define __FPU_PRESENT 0 216 #warning "__FPU_PRESENT not defined in device header file; using default!" 217 #endif 218 219 #ifndef __MPU_PRESENT 220 #define __MPU_PRESENT 0 221 #warning "__MPU_PRESENT not defined in device header file; using default!" 222 #endif 223 224 #ifndef __NVIC_PRIO_BITS 225 #define __NVIC_PRIO_BITS 4 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 227 #endif 228 229 #ifndef __Vendor_SysTickConfig 230 #define __Vendor_SysTickConfig 0 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 232 #endif 233 #endif 234 235 /* IO definitions (access restrictions to peripheral registers) */ 236 /** 237 \defgroup CMSIS_glob_defs CMSIS Global Defines 238 239 <strong>IO Type Qualifiers</strong> are used 240 \li to specify the access to peripheral variables. 241 \li for automatic generation of peripheral register debug information. 242 */ 243 #ifdef __cplusplus 244 #define __I volatile /*!< Defines 'read only' permissions */ 245 #else 246 #define __I volatile const /*!< Defines 'read only' permissions */ 247 #endif 248 #define __O volatile /*!< Defines 'write only' permissions */ 249 #define __IO volatile /*!< Defines 'read / write' permissions */ 250 251 /*@} end of group Cortex_M4 */ 252 253 254 255 /******************************************************************************* 256 * Register Abstraction 257 Core Register contain: 258 - Core Register 259 - Core NVIC Register 260 - Core SCB Register 261 - Core SysTick Register 262 - Core Debug Register 263 - Core MPU Register 264 - Core FPU Register 265 ******************************************************************************/ 266 /** \defgroup CMSIS_core_register Defines and Type Definitions 267 \brief Type definitions and defines for Cortex-M processor based devices. 268 */ 269 270 /** \ingroup CMSIS_core_register 271 \defgroup CMSIS_CORE Status and Control Registers 272 \brief Core Register type definitions. 273 @{ 274 */ 275 276 /** \brief Union type to access the Application Program Status Register (APSR). 277 */ 278 typedef union 279 { 280 struct 281 { 282 #if (__CORTEX_M != 0x04) 283 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 284 #else 285 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 286 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 287 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 288 #endif 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 294 } b; /*!< Structure used for bit access */ 295 uint32_t w; /*!< Type used for word access */ 296 } APSR_Type; 297 298 299 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 300 */ 301 typedef union 302 { 303 struct 304 { 305 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 306 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 307 } b; /*!< Structure used for bit access */ 308 uint32_t w; /*!< Type used for word access */ 309 } IPSR_Type; 310 311 312 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 313 */ 314 typedef union 315 { 316 struct 317 { 318 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 319 #if (__CORTEX_M != 0x04) 320 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 321 #else 322 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 323 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 324 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 325 #endif 326 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 327 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 328 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 329 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 330 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 331 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 332 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 333 } b; /*!< Structure used for bit access */ 334 uint32_t w; /*!< Type used for word access */ 335 } xPSR_Type; 336 337 338 /** \brief Union type to access the Control Registers (CONTROL). 339 */ 340 typedef union 341 { 342 struct 343 { 344 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 345 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 346 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 347 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 348 } b; /*!< Structure used for bit access */ 349 uint32_t w; /*!< Type used for word access */ 350 } CONTROL_Type; 351 352 /*@} end of group CMSIS_CORE */ 353 354 355 /** \ingroup CMSIS_core_register 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 357 \brief Type definitions for the NVIC Registers 358 @{ 359 */ 360 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 362 */ 363 typedef struct 364 { 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 366 uint32_t RESERVED0[24]; 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 368 uint32_t RSERVED1[24]; 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 370 uint32_t RESERVED2[24]; 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 372 uint32_t RESERVED3[24]; 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 374 uint32_t RESERVED4[56]; 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 376 uint32_t RESERVED5[644]; 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 378 } NVIC_Type; 379 380 /* Software Triggered Interrupt Register Definitions */ 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 382 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ 383 384 /*@} end of group CMSIS_NVIC */ 385 386 387 /** \ingroup CMSIS_core_register 388 \defgroup CMSIS_SCB System Control Block (SCB) 389 \brief Type definitions for the System Control Block Registers 390 @{ 391 */ 392 393 /** \brief Structure type to access the System Control Block (SCB). 394 */ 395 typedef struct 396 { 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 416 uint32_t RESERVED0[5]; 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 418 } SCB_Type; 419 420 /* SCB CPUID Register Definitions */ 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 423 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 426 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 429 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 432 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 434 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 435 436 /* SCB Interrupt Control State Register Definitions */ 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 439 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 442 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 445 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 448 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 451 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 454 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 457 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 460 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 463 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 466 467 /* SCB Vector Table Offset Register Definitions */ 468 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 469 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 470 471 /* SCB Application Interrupt and Reset Control Register Definitions */ 472 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 473 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 474 475 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 476 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 477 478 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 480 481 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 483 484 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 485 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 486 487 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 488 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 489 490 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 491 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ 492 493 /* SCB System Control Register Definitions */ 494 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 495 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 496 497 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 498 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 499 500 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 501 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 502 503 /* SCB Configuration Control Register Definitions */ 504 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 505 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 506 507 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 508 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 509 510 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 512 513 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 514 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 515 516 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 517 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 518 519 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 520 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ 521 522 /* SCB System Handler Control and State Register Definitions */ 523 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 524 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 525 526 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 527 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 528 529 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 530 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 531 532 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 533 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 534 535 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 536 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 537 538 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 539 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 540 541 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 542 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 543 544 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 545 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 546 547 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 548 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 549 550 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 551 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 552 553 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 554 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 555 556 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 557 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 558 559 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 560 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 561 562 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 563 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ 564 565 /* SCB Configurable Fault Status Registers Definitions */ 566 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 567 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 568 569 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 570 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 571 572 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 573 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 574 575 /* SCB Hard Fault Status Registers Definitions */ 576 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 577 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 578 579 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 580 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 581 582 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 583 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 584 585 /* SCB Debug Fault Status Register Definitions */ 586 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 587 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 588 589 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 590 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 591 592 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 593 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 594 595 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 596 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 597 598 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 599 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ 600 601 /*@} end of group CMSIS_SCB */ 602 603 604 /** \ingroup CMSIS_core_register 605 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 606 \brief Type definitions for the System Control and ID Register not in the SCB 607 @{ 608 */ 609 610 /** \brief Structure type to access the System Control and ID Register not in the SCB. 611 */ 612 typedef struct 613 { 614 uint32_t RESERVED0[1]; 615 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 616 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 617 } SCnSCB_Type; 618 619 /* Interrupt Controller Type Register Definitions */ 620 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 621 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ 622 623 /* Auxiliary Control Register Definitions */ 624 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ 625 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 626 627 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ 628 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 629 630 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 631 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 632 633 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ 634 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 635 636 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 637 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 638 639 /*@} end of group CMSIS_SCnotSCB */ 640 641 642 /** \ingroup CMSIS_core_register 643 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 644 \brief Type definitions for the System Timer Registers. 645 @{ 646 */ 647 648 /** \brief Structure type to access the System Timer (SysTick). 649 */ 650 typedef struct 651 { 652 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 653 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 654 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 655 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 656 } SysTick_Type; 657 658 /* SysTick Control / Status Register Definitions */ 659 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 660 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 661 662 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 663 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 664 665 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 666 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 667 668 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 669 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 670 671 /* SysTick Reload Register Definitions */ 672 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 673 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 674 675 /* SysTick Current Register Definitions */ 676 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 677 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 678 679 /* SysTick Calibration Register Definitions */ 680 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 681 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 682 683 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 684 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 685 686 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 687 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 688 689 /*@} end of group CMSIS_SysTick */ 690 691 692 /** \ingroup CMSIS_core_register 693 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 694 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 695 @{ 696 */ 697 698 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 699 */ 700 typedef struct 701 { 702 __O union 703 { 704 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 705 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 706 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 707 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 708 uint32_t RESERVED0[864]; 709 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 710 uint32_t RESERVED1[15]; 711 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 712 uint32_t RESERVED2[15]; 713 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 714 uint32_t RESERVED3[29]; 715 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 716 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 717 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 718 uint32_t RESERVED4[43]; 719 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 720 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 721 uint32_t RESERVED5[6]; 722 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 723 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 724 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 725 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 726 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 727 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 728 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 729 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 730 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 731 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 732 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 733 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 734 } ITM_Type; 735 736 /* ITM Trace Privilege Register Definitions */ 737 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 738 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ 739 740 /* ITM Trace Control Register Definitions */ 741 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 742 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 743 744 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 745 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 746 747 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 748 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 749 750 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 751 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 752 753 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 754 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 755 756 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 757 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 758 759 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 760 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 761 762 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 763 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 764 765 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 766 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ 767 768 /* ITM Integration Write Register Definitions */ 769 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 770 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ 771 772 /* ITM Integration Read Register Definitions */ 773 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 774 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ 775 776 /* ITM Integration Mode Control Register Definitions */ 777 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 778 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ 779 780 /* ITM Lock Status Register Definitions */ 781 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 782 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 783 784 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 785 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 786 787 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 788 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ 789 790 /*@}*/ /* end of group CMSIS_ITM */ 791 792 793 /** \ingroup CMSIS_core_register 794 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 795 \brief Type definitions for the Data Watchpoint and Trace (DWT) 796 @{ 797 */ 798 799 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 800 */ 801 typedef struct 802 { 803 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 804 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 805 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 806 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 807 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 808 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 809 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 810 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 811 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 812 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 813 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 814 uint32_t RESERVED0[1]; 815 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 816 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 817 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 818 uint32_t RESERVED1[1]; 819 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 820 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 821 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 822 uint32_t RESERVED2[1]; 823 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 824 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 825 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 826 } DWT_Type; 827 828 /* DWT Control Register Definitions */ 829 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ 830 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 831 832 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ 833 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 834 835 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ 836 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 837 838 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ 839 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 840 841 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ 842 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 843 844 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ 845 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 846 847 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ 848 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 849 850 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ 851 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 852 853 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ 854 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 855 856 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ 857 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 858 859 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ 860 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 861 862 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ 863 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 864 865 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ 866 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 867 868 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ 869 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 870 871 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ 872 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 873 874 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ 875 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 876 877 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ 878 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 879 880 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ 881 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ 882 883 /* DWT CPI Count Register Definitions */ 884 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ 885 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ 886 887 /* DWT Exception Overhead Count Register Definitions */ 888 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ 889 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ 890 891 /* DWT Sleep Count Register Definitions */ 892 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ 893 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 894 895 /* DWT LSU Count Register Definitions */ 896 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ 897 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ 898 899 /* DWT Folded-instruction Count Register Definitions */ 900 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ 901 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ 902 903 /* DWT Comparator Mask Register Definitions */ 904 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ 905 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ 906 907 /* DWT Comparator Function Register Definitions */ 908 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ 909 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 910 911 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ 912 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 913 914 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ 915 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 916 917 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ 918 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 919 920 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ 921 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 922 923 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ 924 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 925 926 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ 927 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 928 929 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ 930 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 931 932 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ 933 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ 934 935 /*@}*/ /* end of group CMSIS_DWT */ 936 937 938 /** \ingroup CMSIS_core_register 939 \defgroup CMSIS_TPI Trace Port Interface (TPI) 940 \brief Type definitions for the Trace Port Interface (TPI) 941 @{ 942 */ 943 944 /** \brief Structure type to access the Trace Port Interface Register (TPI). 945 */ 946 typedef struct 947 { 948 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 949 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 950 uint32_t RESERVED0[2]; 951 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 952 uint32_t RESERVED1[55]; 953 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 954 uint32_t RESERVED2[131]; 955 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 956 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 957 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 958 uint32_t RESERVED3[759]; 959 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 960 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 961 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 962 uint32_t RESERVED4[1]; 963 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 964 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 965 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 966 uint32_t RESERVED5[39]; 967 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 968 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 969 uint32_t RESERVED7[8]; 970 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 971 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 972 } TPI_Type; 973 974 /* TPI Asynchronous Clock Prescaler Register Definitions */ 975 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ 976 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ 977 978 /* TPI Selected Pin Protocol Register Definitions */ 979 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ 980 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ 981 982 /* TPI Formatter and Flush Status Register Definitions */ 983 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ 984 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 985 986 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ 987 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 988 989 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ 990 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 991 992 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ 993 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ 994 995 /* TPI Formatter and Flush Control Register Definitions */ 996 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ 997 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 998 999 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ 1000 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1001 1002 /* TPI TRIGGER Register Definitions */ 1003 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ 1004 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ 1005 1006 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1007 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ 1008 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 1009 1010 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ 1011 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 1012 1013 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ 1014 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 1015 1016 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ 1017 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 1018 1019 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ 1020 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 1021 1022 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ 1023 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 1024 1025 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ 1026 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ 1027 1028 /* TPI ITATBCTR2 Register Definitions */ 1029 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ 1030 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ 1031 1032 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1033 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ 1034 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 1035 1036 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ 1037 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 1038 1039 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ 1040 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 1041 1042 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ 1043 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 1044 1045 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ 1046 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 1047 1048 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ 1049 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 1050 1051 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ 1052 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ 1053 1054 /* TPI ITATBCTR0 Register Definitions */ 1055 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ 1056 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ 1057 1058 /* TPI Integration Mode Control Register Definitions */ 1059 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ 1060 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ 1061 1062 /* TPI DEVID Register Definitions */ 1063 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ 1064 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1065 1066 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ 1067 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1068 1069 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ 1070 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1071 1072 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ 1073 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 1074 1075 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ 1076 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 1077 1078 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ 1079 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ 1080 1081 /* TPI DEVTYPE Register Definitions */ 1082 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ 1083 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ 1084 1085 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ 1086 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1087 1088 /*@}*/ /* end of group CMSIS_TPI */ 1089 1090 1091 #if (__MPU_PRESENT == 1) 1092 /** \ingroup CMSIS_core_register 1093 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1094 \brief Type definitions for the Memory Protection Unit (MPU) 1095 @{ 1096 */ 1097 1098 /** \brief Structure type to access the Memory Protection Unit (MPU). 1099 */ 1100 typedef struct 1101 { 1102 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1103 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1104 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1105 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1106 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 1107 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 1108 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 1109 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 1110 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 1111 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 1112 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 1113 } MPU_Type; 1114 1115 /* MPU Type Register */ 1116 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 1117 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1118 1119 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 1120 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1121 1122 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 1123 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 1124 1125 /* MPU Control Register */ 1126 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 1127 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1128 1129 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 1130 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1131 1132 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 1133 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 1134 1135 /* MPU Region Number Register */ 1136 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 1137 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 1138 1139 /* MPU Region Base Address Register */ 1140 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 1141 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1142 1143 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 1144 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1145 1146 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 1147 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 1148 1149 /* MPU Region Attribute and Size Register */ 1150 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 1151 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1152 1153 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 1154 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1155 1156 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 1157 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1158 1159 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 1160 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1161 1162 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 1163 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 1164 1165 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 1166 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 1167 1168 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 1169 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 1170 1171 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 1172 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 1173 1174 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 1175 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 1176 1177 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 1178 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 1179 1180 /*@} end of group CMSIS_MPU */ 1181 #endif 1182 1183 1184 #if (__FPU_PRESENT == 1) 1185 /** \ingroup CMSIS_core_register 1186 \defgroup CMSIS_FPU Floating Point Unit (FPU) 1187 \brief Type definitions for the Floating Point Unit (FPU) 1188 @{ 1189 */ 1190 1191 /** \brief Structure type to access the Floating Point Unit (FPU). 1192 */ 1193 typedef struct 1194 { 1195 uint32_t RESERVED0[1]; 1196 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 1197 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 1198 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 1199 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 1200 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 1201 } FPU_Type; 1202 1203 /* Floating-Point Context Control Register */ 1204 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ 1205 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1206 1207 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ 1208 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1209 1210 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ 1211 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1212 1213 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ 1214 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1215 1216 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ 1217 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 1218 1219 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ 1220 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 1221 1222 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ 1223 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 1224 1225 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ 1226 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 1227 1228 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ 1229 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ 1230 1231 /* Floating-Point Context Address Register */ 1232 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ 1233 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 1234 1235 /* Floating-Point Default Status Control Register */ 1236 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ 1237 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 1238 1239 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ 1240 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 1241 1242 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ 1243 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 1244 1245 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ 1246 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 1247 1248 /* Media and FP Feature Register 0 */ 1249 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ 1250 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 1251 1252 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ 1253 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 1254 1255 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ 1256 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 1257 1258 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ 1259 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 1260 1261 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ 1262 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 1263 1264 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ 1265 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 1266 1267 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ 1268 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 1269 1270 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ 1271 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ 1272 1273 /* Media and FP Feature Register 1 */ 1274 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ 1275 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 1276 1277 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ 1278 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1279 1280 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ 1281 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1282 1283 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ 1284 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ 1285 1286 /*@} end of group CMSIS_FPU */ 1287 #endif 1288 1289 1290 /** \ingroup CMSIS_core_register 1291 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1292 \brief Type definitions for the Core Debug Registers 1293 @{ 1294 */ 1295 1296 /** \brief Structure type to access the Core Debug Register (CoreDebug). 1297 */ 1298 typedef struct 1299 { 1300 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1301 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1302 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1303 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1304 } CoreDebug_Type; 1305 1306 /* Debug Halting Control and Status Register */ 1307 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 1308 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1309 1310 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1311 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1312 1313 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1314 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1315 1316 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1317 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1318 1319 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 1320 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1321 1322 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 1323 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1324 1325 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 1326 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1327 1328 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1329 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1330 1331 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1332 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1333 1334 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 1335 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1336 1337 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 1338 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1339 1340 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1341 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1342 1343 /* Debug Core Register Selector Register */ 1344 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 1345 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1346 1347 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 1348 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ 1349 1350 /* Debug Exception and Monitor Control Register */ 1351 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 1352 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1353 1354 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 1355 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1356 1357 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 1358 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1359 1360 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 1361 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1362 1363 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 1364 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1365 1366 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1367 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1368 1369 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 1370 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1371 1372 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1373 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1374 1375 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 1376 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1377 1378 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1379 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1380 1381 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1382 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1383 1384 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 1385 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1386 1387 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1388 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1389 1390 /*@} end of group CMSIS_CoreDebug */ 1391 1392 1393 /** \ingroup CMSIS_core_register 1394 \defgroup CMSIS_core_base Core Definitions 1395 \brief Definitions for base addresses, unions, and structures. 1396 @{ 1397 */ 1398 1399 /* Memory mapping of Cortex-M4 Hardware */ 1400 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1401 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1402 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1403 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1404 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1405 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1406 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1407 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1408 1409 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1410 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1411 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1412 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1413 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1414 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1415 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1416 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 1417 1418 #if (__MPU_PRESENT == 1) 1419 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1420 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1421 #endif 1422 1423 #if (__FPU_PRESENT == 1) 1424 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1425 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1426 #endif 1427 1428 /*@} */ 1429 1430 1431 1432 /******************************************************************************* 1433 * Hardware Abstraction Layer 1434 Core Function Interface contains: 1435 - Core NVIC Functions 1436 - Core SysTick Functions 1437 - Core Debug Functions 1438 - Core Register Access Functions 1439 ******************************************************************************/ 1440 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1441 */ 1442 1443 1444 1445 /* ########################## NVIC functions #################################### */ 1446 /** \ingroup CMSIS_Core_FunctionInterface 1447 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1448 \brief Functions that manage interrupts and exceptions via the NVIC. 1449 @{ 1450 */ 1451 1452 /** \brief Set Priority Grouping 1453 1454 The function sets the priority grouping field using the required unlock sequence. 1455 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1456 Only values from 0..7 are used. 1457 In case of a conflict between priority grouping and available 1458 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1459 1460 \param [in] PriorityGroup Priority grouping field. 1461 */ 1462 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1463 { 1464 uint32_t reg_value; 1465 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 1466 1467 reg_value = SCB->AIRCR; /* read old register configuration */ 1468 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 1469 reg_value = (reg_value | 1470 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 1471 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 1472 SCB->AIRCR = reg_value; 1473 } 1474 1475 1476 /** \brief Get Priority Grouping 1477 1478 The function reads the priority grouping field from the NVIC Interrupt Controller. 1479 1480 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1481 */ 1482 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 1483 { 1484 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 1485 } 1486 1487 1488 /** \brief Enable External Interrupt 1489 1490 The function enables a device-specific interrupt in the NVIC interrupt controller. 1491 1492 \param [in] IRQn External interrupt number. Value cannot be negative. 1493 */ 1494 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 1495 { 1496 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ 1497 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ 1498 } 1499 1500 1501 /** \brief Disable External Interrupt 1502 1503 The function disables a device-specific interrupt in the NVIC interrupt controller. 1504 1505 \param [in] IRQn External interrupt number. Value cannot be negative. 1506 */ 1507 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 1508 { 1509 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 1510 } 1511 1512 1513 /** \brief Get Pending Interrupt 1514 1515 The function reads the pending register in the NVIC and returns the pending bit 1516 for the specified interrupt. 1517 1518 \param [in] IRQn Interrupt number. 1519 1520 \return 0 Interrupt status is not pending. 1521 \return 1 Interrupt status is pending. 1522 */ 1523 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 1524 { 1525 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 1526 } 1527 1528 1529 /** \brief Set Pending Interrupt 1530 1531 The function sets the pending bit of an external interrupt. 1532 1533 \param [in] IRQn Interrupt number. Value cannot be negative. 1534 */ 1535 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 1536 { 1537 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 1538 } 1539 1540 1541 /** \brief Clear Pending Interrupt 1542 1543 The function clears the pending bit of an external interrupt. 1544 1545 \param [in] IRQn External interrupt number. Value cannot be negative. 1546 */ 1547 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1548 { 1549 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 1550 } 1551 1552 1553 /** \brief Get Active Interrupt 1554 1555 The function reads the active register in NVIC and returns the active bit. 1556 1557 \param [in] IRQn Interrupt number. 1558 1559 \return 0 Interrupt status is not active. 1560 \return 1 Interrupt status is active. 1561 */ 1562 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 1563 { 1564 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 1565 } 1566 1567 1568 /** \brief Set Interrupt Priority 1569 1570 The function sets the priority of an interrupt. 1571 1572 \note The priority cannot be set for every core interrupt. 1573 1574 \param [in] IRQn Interrupt number. 1575 \param [in] priority Priority to set. 1576 */ 1577 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1578 { 1579 if(IRQn < 0) { 1580 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 1581 else { 1582 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 1583 } 1584 1585 1586 /** \brief Get Interrupt Priority 1587 1588 The function reads the priority of an interrupt. The interrupt 1589 number can be positive to specify an external (device specific) 1590 interrupt, or negative to specify an internal (core) interrupt. 1591 1592 1593 \param [in] IRQn Interrupt number. 1594 \return Interrupt Priority. Value is aligned automatically to the implemented 1595 priority bits of the microcontroller. 1596 */ 1597 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 1598 { 1599 1600 if(IRQn < 0) { 1601 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 1602 else { 1603 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 1604 } 1605 1606 1607 /** \brief Encode Priority 1608 1609 The function encodes the priority for an interrupt with the given priority group, 1610 preemptive priority value, and subpriority value. 1611 In case of a conflict between priority grouping and available 1612 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1613 1614 \param [in] PriorityGroup Used priority group. 1615 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1616 \param [in] SubPriority Subpriority value (starting from 0). 1617 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1618 */ 1619 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1620 { 1621 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1622 uint32_t PreemptPriorityBits; 1623 uint32_t SubPriorityBits; 1624 1625 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1626 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1627 1628 return ( 1629 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 1630 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 1631 ); 1632 } 1633 1634 1635 /** \brief Decode Priority 1636 1637 The function decodes an interrupt priority value with a given priority group to 1638 preemptive priority value and subpriority value. 1639 In case of a conflict between priority grouping and available 1640 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1641 1642 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1643 \param [in] PriorityGroup Used priority group. 1644 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1645 \param [out] pSubPriority Subpriority value (starting from 0). 1646 */ 1647 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 1648 { 1649 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1650 uint32_t PreemptPriorityBits; 1651 uint32_t SubPriorityBits; 1652 1653 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1654 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1655 1656 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 1657 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 1658 } 1659 1660 1661 /** \brief System Reset 1662 1663 The function initiates a system reset request to reset the MCU. 1664 */ 1665 __STATIC_INLINE void NVIC_SystemReset(void) 1666 { 1667 __DSB(); /* Ensure all outstanding memory accesses included 1668 buffered write are completed before reset */ 1669 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 1670 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1671 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 1672 __DSB(); /* Ensure completion of memory access */ 1673 while(1); /* wait until reset */ 1674 } 1675 1676 /*@} end of CMSIS_Core_NVICFunctions */ 1677 1678 1679 1680 /* ################################## SysTick function ############################################ */ 1681 /** \ingroup CMSIS_Core_FunctionInterface 1682 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1683 \brief Functions that configure the System. 1684 @{ 1685 */ 1686 1687 #if (__Vendor_SysTickConfig == 0) 1688 1689 /** \brief System Tick Configuration 1690 1691 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 1692 Counter is in free running mode to generate periodic interrupts. 1693 1694 \param [in] ticks Number of ticks between two interrupts. 1695 1696 \return 0 Function succeeded. 1697 \return 1 Function failed. 1698 1699 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1700 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1701 must contain a vendor-specific implementation of this function. 1702 1703 */ 1704 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1705 { 1706 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 1707 1708 SysTick->LOAD = ticks - 1; /* set reload register */ 1709 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 1710 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 1711 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1712 SysTick_CTRL_TICKINT_Msk | 1713 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1714 return (0); /* Function successful */ 1715 } 1716 1717 #endif 1718 1719 /*@} end of CMSIS_Core_SysTickFunctions */ 1720 1721 1722 1723 /* ##################################### Debug In/Output function ########################################### */ 1724 /** \ingroup CMSIS_Core_FunctionInterface 1725 \defgroup CMSIS_core_DebugFunctions ITM Functions 1726 \brief Functions that access the ITM debug interface. 1727 @{ 1728 */ 1729 1730 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 1731 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 1732 1733 1734 /** \brief ITM Send Character 1735 1736 The function transmits a character via the ITM channel 0, and 1737 \li Just returns when no debugger is connected that has booked the output. 1738 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 1739 1740 \param [in] ch Character to transmit. 1741 1742 \returns Character to transmit. 1743 */ 1744 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 1745 { 1746 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 1747 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 1748 { 1749 while (ITM->PORT[0].u32 == 0); 1750 ITM->PORT[0].u8 = (uint8_t) ch; 1751 } 1752 return (ch); 1753 } 1754 1755 1756 /** \brief ITM Receive Character 1757 1758 The function inputs a character via the external variable \ref ITM_RxBuffer. 1759 1760 \return Received character. 1761 \return -1 No character pending. 1762 */ 1763 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 1764 int32_t ch = -1; /* no character available */ 1765 1766 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 1767 ch = ITM_RxBuffer; 1768 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 1769 } 1770 1771 return (ch); 1772 } 1773 1774 1775 /** \brief ITM Check Character 1776 1777 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 1778 1779 \return 0 No character available. 1780 \return 1 Character available. 1781 */ 1782 __STATIC_INLINE int32_t ITM_CheckChar (void) { 1783 1784 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 1785 return (0); /* no character available */ 1786 } else { 1787 return (1); /* character available */ 1788 } 1789 } 1790 1791 /*@} end of CMSIS_core_DebugFunctions */ 1792 1793 1794 1795 1796 #ifdef __cplusplus 1797 } 1798 #endif 1799 1800 #endif /* __CORE_CM4_H_DEPENDANT */ 1801 1802 #endif /* __CMSIS_GENERIC */ 1803
